Elegant Additional Materials 9 17 2026 Final.pdf

This document provides additional program design information for ELEGANT proposers. Some of the criteria included here are intended to be illustrative. They may change as a result of the OTASO proposal and negotiation process and/or refinement through the Annual Project Plan (APP) approval process.

ELEGANT Translation Themes ELEGANT is organized around five Translation Themes. Each Theme is defined by its Translation Endpoint — the industry-adoptable deliverable against which Expert Performer Teams (EPTs) are selected and held accountable. Go/No-Go criteria are Phase-end checkpoints assessing whether each Team has made sufficient progress to justify continued NSF investment;

meeting a criterion confirms continued funding, while achieving the Translation Endpoint confirms the Theme has fulfilled its program purpose. Criteria are established at pre-award and may be refined through the Annual Project Plan process, consistent with Section 4.2. Some of the details listed below are illustrative; EPTs are expected to identify the most effective approach to achieving each Theme's endpoint and the overall Translation Endpoint of a full-chip demonstration as defined below at the end of Theme 3.

Theme 1 — Manufacturable Materials Platform

Translation Endpoint: Demonstrate Low-D semiconductor materials using uniform wafer-scale or selective-area synthesis/deposition — that meet industry-defined specifications at both 200 mm and 300 mm wafers, using production-relevant deposition equipment to synthesize the material and production-relevant metrology equipment to characterize it, both on a pathway to manufacturing readiness. Success requires industry partner sign-off confirming specifications are met at both wafer sizes, with both deposition and metrology processes and equipment on a demonstrated production pathway — not synthesis- and metrology-science advances alone.

• Industry-Defined Low-D Semiconductor Material Quality Specifications. Establish, maintain and refine advanced-node material specifications with two or more industry partners, including requirements for quality, uniformity, defects, and surface/interface properties, applicable at both 200 mm and 300 mm. Initial specifications will be documented in the Annual Project Plan (APP) and refined during Phase 1.

• Wafer-Scale Material Growth. Scalable Low-D material synthesis meeting the industry-defined quality specifications, via uniform and/or selective-area growth, at both 200 mm and 300 mm, using production-worthy methods including (but not limited to) CVD, MOCVD, ALD, MBE or hybrid methods. Competing approaches operate in parallel through Go/No-Go 1, with down-selection based on the ability to meet or exceed the industry-defined specifications at 200 mm.

• Deposition Equipment Development and Qualification. Deposition tools for high-quality uniform and/or selective-area synthesis, scaled to both 200 mm and 300 mm and meeting industry adoption criteria by end of Phase 2, with demonstrated reproducibility and manufacturing readiness.

• Metrology Equipment Development and Qualification. High-throughput, non-destructive industry-relevant metrology equipment for characterization of materials including measuring thickness uniformity, stoichiometry, and surface cleanliness, scaled to both 200 mm and 300 mm and meeting industry adoption criteria by end of Phase 2.

• AI-Acceleration. Theme 5 AI/ML applied to synthesis/deposition parameter optimization and tool development.

Go/No-Go 1 (End of Phase 1): Material growth and metrology meet specifications at 200 mm, validated by two or more industry partners; interim deposition/metrology tools sufficient to support Phase 2 development at 300 mm and Themes 2–3. Non-qualifying approaches terminated; survivors may be intensified.

Go/No-Go 2 (End of Phase 2): Materials at 300 mm fully meet specifications under production-relevant conditions, with written feedback from three or more industry partners; deposition tools matured to production-relevant 300 mm capability, and metrology tools matured to production-relevant 300 mm capability, both sufficient to support Phase 3 integration.

Go/No-Go 3 (End of Phase 3): Translation Endpoint achieved: industry partners and EPTs agree that material quality, yield, consistency, and throughput at both 200 mm and 300 mm are sufficient to support Endpoints for Themes 2–4. Deposition tools and metrology tools each independently meet industry and roadmap criteria; two or more tool-manufacturing partners confirm in writing that the technology meets their qualification-program criteria, with at least one industry partner committing to fund Phase 4.

Theme 2 — Process Technology & PDK

Translation Endpoint: A documented, reproducible process flow and PDK — incorporating unit process steps including etch, dielectric, doping, passivation, and contact processes meeting industry-defined specifications at 300 mm — released to two or more independent industry partners and sufficient for circuit-level design and evaluation of Low-D devices. Theme 2 translates Theme 1 material advances into a manufacturable process platform for device and circuit implementation (in Theme 3).

• Industry-Defined Process Specifications. Establish, maintain and refine specifications for unit process steps — including etch, dielectric, doping, passivation, and contact processes — and process flows, with two or more industry partners, aligned with Theme 1 material specifications.

• Process Development. Development of the unit process steps and process flows needed to meet the specifications above — including minimizing contact resistance and addressing Fermi-level pinning, doping approaches suited to Low-D materials and process conditions compatible with the thermal budget constraints of Low-D materials — with two or more industry partners validating processes.

• Process Qualification. Qualification of unit process steps (and equipment) at 300 mm, meeting the specifications above and validated by two or more industry partners.

• Process Integration. Full-flow integration, including process-of-record documentation sufficient for industry adoption, with two or more industry partners validating process integration results.

• PDK Development and Release. Develop design rules, device models, and layout-verification tools forming a releasable PDK, followed by PDK hardening (design-rule verification, compact-model refinement, layout verification).

• Metrology Feedback Integration. Theme 1 metrology data fed into process-control loops for optimization/stability monitoring.

• AI-Accelerated Process Optimization. Theme 5 AI/ML applied to process-parameter optimization, defect reduction, and yield improvement.

Go/No-Go 1 (End of Phase 1): Viable initial unit-process specifications established with two or more industry partners, and a preliminary integration framework sufficient to support full-flow process development in Phase 2. Interim unit-process capability sufficient to support Theme 1 selective-area teams' own Go/No-Go 1. Criteria refined via Phase 1 APP.

Go/No-Go 2 (End of Phase 2): PDK released to two or more independent industry partners, each providing written confirmation to NSF that the PDK meets its internal circuit-design-initiation criteria; process flows documented sufficiently for industry circuit design; processes meet specifications, with written feedback from three or more industry partners. This is program-defining criteria and is not reducible via pre-award negotiation.

Go/No-Go 3 (End of Phase 3): Translation Endpoint substantially achieved: (i) process flows hardened to process-of-record standards, independently verified — building on the preliminary process-of-record documentation established at Process Integration; (ii) PDK matured beyond Go/No-Go 2 via industry validation and partner feedback — design-rule verification, refined compact models, and layout-verification tools sufficient for independent use; (iii) two or more Go/No-Go 2 PDK recipients have completed or substantially advanced an internal circuit-design project using it; (iv) etch, dielectric, doping, passivation, and contact processes meet specifications under production-relevant (300 mm) conditions, with equipment qualification meeting roadmap criteria and written confirmation from two or more tool-manufacturing partners, at least one of whom commits to fund Phase 4.

Theme 3 — Device, Circuit and Full-Chip Demonstration

Translation Endpoint: Functional qualification-level full-chip prototypes demonstrating at least a 10X PPAC improvement relative to a relevant CMOS technology node, validated by two or more independent industry partners. This Theme is ELEGANT's primary proof point for industrial adoption readiness. The 10X PPAC demonstration defines whether Low-D semiconductor technology has reached the state where industry can make an evidence-based adoption decision. Theme 3 is back-loaded: spend rises from Phase 1 through Phases 2 and 3 with chip-level fabrication and industry validation — the most cost-intensive activities — occurring in later Phases.

• Device Architecture Optimization. Design and validation of transistor architectures with optimized electrostatics, scaling behavior, and contact performance, benchmarked against advanced CMOS. The primary device architectures will be down-selected at Go/No-Go 1 based on performance, manufacturability, and commercial pathway credibility.

• EDA Tools and Compact Models. Compact physics-based models (SPICE/Verilog-A), AI-assisted circuit optimization, variability-aware simulation, and DRC/LVS tools integrated with the Theme 2 PDK.

• Circuit and ASIC Fabrication. Functional circuits and full-chip-level prototypes using Theme 2 process flows; CMOS-compatible BEOL co-integration; wafer-scale statistical characterization of variability, yield, and performance.

• Demonstration Vehicles. May include SRAM-class embedded memory macros, AI inference accelerator tiles, logic standard-cell blocks, or other chip-level implementations providing a credible and quantitative basis for industrial adoption. The reference CMOS node for the 10X PPAC measurement will be established at pre-award negotiation (including the necessary foundry and manufacturing conditions).

• Industry Validation. Direct engagement with two or more independent industry partners for chip-level evaluation against NSF-approved power-performance-area-cost (PPAC) benchmarks and qualification criteria, resulting in written confirmation that evaluation has been completed and/or qualification initiated. Demonstrations shall be supported by wafer-scale (300 mm) statistical characterization, validated against industry- and defense-relevant benchmarks.

• Secondary Applications. Demonstrations addressing RF and millimeter-wave circuits, power switching, or sensing and imaging are viewed favorably where clearly complementary to and not displacing the primary advanced-node objective.

• AI-Accelerated Design Optimization. Application of Theme 5 AI/ML platforms to device and circuit optimization, yield improvement, and design space exploration.

Go/No-Go 1 (End of Phase 1): Theme 3 will establish and refine a preliminary set of device design rules and architectures beginning early in Phase 1 using Theme 3’s foundational development work, then updated as results become available from Themes 1 and 2— sufficient to select a primary architecture direction for Phase 2. NSF will down-select to the most promising direction(s) based on performance, manufacturability, and commercial pathway credibility; non-selected approaches will be de-scoped. Specific criteria, including hand-off timing from Themes 1 and 2, will be established through the Annual Project Plan process for Phase 1.

Go/No-Go 2 (End of Phase 2): Architectures selected at Go/No-Go 1 have demonstrated transistor-level performance sufficient to justify advancement to full-chip fabrication in Phase 3.

Specific criteria will be established and refined through the Annual Project Plan process for Phase 2.

Go/No-Go 3 (End of Phase 3): Functional full-chip prototypes achieving at least a 10X PPAC improvement versus the agreed reference CMOS node have been demonstrated and independently verified by two or more industry partners. In addition, at least two independent industry partners must have provided written confirmation that the demonstrated technology meets their minimum criteria for initiating a technology evaluation and/or qualification program, and at least one must have committed to co-fund Phase 4 activities. The 10X PPAC threshold, two-partner validation requirement, and Phase 4 co-funding commitment are program-defining milestones and will apply as stated regardless of awardee.

Theme 4 — Manufacturing Readiness & Transition

Translation Endpoint: A manufacturing readiness capability — comprising a cost and yield model, foundation for a domestic supply chain, and minimal packaging solution — providing the information industry needs to make a capital investment decision in Low-D semiconductor technology. The deliverable is not a research report but actionable capabilities for industry decision-makers to assess production feasibility and initiate capital planning. Theme 4 is expected to operate as a single integrated effort, with a relatively even spend profile as its activities run in parallel with all other Themes throughout the program.

• 300 mm Tool Qualification Roadmap. Engagement with domestic equipment manufacturers on tool development, adaptation, and qualification for 300 mm manufacturing; identification of tool gaps and resolution pathways; coordination with Theme 1 deposition tool activities.

• Packaging and Interconnects. Minimal adaptation and demonstration of existing and/or commercially available packaging approaches at a level sufficient for the full-chip level demonstration.

• Cost and Yield Modeling. Manufacturing cost and yield analysis demonstrating a credible pathway to cost-competitive high-volume manufacturing, with key cost drivers and yield loss mechanisms identified and quantified at each program Phase.

• Domestic Supply Chain. Identification and preliminary qualification of domestic suppliers for key precursor materials, substrates, and equipment; characterization of single-source dependencies and mitigation strategies; coordination with the Ecosystem Coordinator's Technology Roadmapping activities.

• Industry Phase 4 Commitment. Theme 4 culminates in the manufacturing readiness package supporting an industry Phase 4 manufacturing funding decision. Early industry assumption of funding for Theme 4 elements prior to end of Phase 3 is strongly encouraged and tracked as a leading indicator of translation success.

Go/No-Go 1 (End of Phase 1): Theme 4 has completed preliminary supply chain mapping, initiated engagement with at least two domestic equipment manufacturers, and established a cost and yield modeling framework sufficient to support Phase 2 manufacturing analysis. Specific criteria will be established and refined through the Annual Project Plan process for Phase 1.

Go/No-Go 2 (End of Phase 2): The Theme 4 manufacturing analysis has progressed sufficiently

— including updated cost and yield models reflecting Phase 2 process data and initial supplier qualification — to support completion of the full manufacturing readiness package in Phase 3.

Specific criteria will be established and refined through the Annual Project Plan process for Phase 2.

Go/No-Go 3 (End of Phase 3): A complete manufacturing readiness capability has been developed and delivered comprising: (i) a 300 mm tool qualification roadmap reviewed by at least two domestic equipment manufacturers; (ii) a manufacturing cost and yield model validated against Phase 3 process data; (iii) a domestic supply chain assessment identifying qualified or qualifiable suppliers for key precursor materials and tooling; and (iv) a demonstrated packaging approach using Theme 3 device outputs. These capabilities have been reviewed by at least two independent industry partners, each providing written confirmation that the manufacturing readiness capability supplies sufficient information to initiate an internal production feasibility assessment. These requirements are program-defining and will apply as stated regardless of awardee.

Theme 5 — AI-Enabled Acceleration

Translation Endpoint: A shared AI/ML platform demonstrating measurable reduction in time-to-result across at least three of Themes 1–3, with validated closed-loop learning deployed in at least one materials synthesis and process development workflow by end of Phase 2. Theme 5 delivers the AI/ML infrastructure accelerating the technology development Themes. All models are developed in direct support of other EPTs' technical needs and validated against experimental results and industry assessments, not as standalone research outputs, so that model development is driven by — and its outputs are usable by — the Themes that depend on them.

Theme 5 EPT(s) will work closely with the Ecosystem Coordinator to ensure effective coordination and alignment among Theme 5 performers and the EPTs across the other Themes.

• Shared AI/ML Platform. Configure and administer a shared AI/ML platform for ELEGANT, built on existing infrastructure rather than developed from scratch. The platform will provide common data schemas, model registries, and API interfaces, enabling EPTs to contribute data and consume model outputs without duplicating infrastructure investments. Existing resources should be leveraged as appropriate. The shared AI/ML platform will be operated, maintained, and continuously improved through Phase 3. Platform utilization and demonstrated acceleration of research workflows will be reported to NSF through each Annual Project Plan.

• Materials Discovery and Synthesis Optimization. Develop and apply AI/ML models for materials-property prediction, synthesis-parameter optimization, and alloy engineering in support of Theme 1 Expert Performer Team(s).

• Etch, Dielectric, Doping, Passivation, and Contact Engineering. Develop and apply AI/ML models for etching, dielectric, passivation, and doping processes, including dopant–host screening and doping-strategy development. Develop models for contact engineering, including prediction of Schottky barriers and Fermi-level pinning and screening of contact metals and geometries, to support wafer-scale uniformity prediction by Theme 2 Expert Performer Team(s).

• Process Optimization and Defect Reduction. AI/ML models for process parameter optimization, defect classification, yield optimization used by Theme 2 and 3 Expert Performer Team(s).

• Device Architecture, EDA, and Circuit Design. Develop and apply AI/ML models spanning device-level simulation and structure optimization through circuit-level design, including performance prediction, design-rule and layout optimization, PDK development support, device–circuit co-design, variability-aware circuit sizing, and standard-cell characterization in support of Theme 3 Expert Performer Team(s).

• Closed-Loop Learning Integration. Deployment of industry-validated closed-loop learning workflows in which AI model outputs directly inform experimental parameters in subsequent synthesis and process runsnabling iterative learning and accelerated optimization across the ELEGANT workflow.

Go/No-Go 1 (End of Phase 1): The AI/ML platform has been deployed and is accessible to all EPTs, with initial data pipelines operational for at least two of Themes 1-3. At least one industry partner has validated the AI/ML platform.

Go/No-Go 2 (End of Phase 2): The AI/ML platform is actively used by three EPTs for at least two of Themes 1-3 and at least one validated closed-loop learning workflow has been demonstrated with documented reduction in experimental iterations or time-to-result compared to baseline. NSF will assess whether continued Phase 3 investment at current levels is warranted based on demonstrated acceleration value across the program.

Go/No-Go 3 (End of Phase 3): The AI/ML platform has delivered measurable acceleration across three Themes 1-3 throughout Phase 3, as documented in the platform's performance reporting. Specific acceleration metrics will be established and refined through the Annual Project Plan process for Phase 3.

ELEGANT Ecosystem Coordinator Translation Endpoint. The Ecosystem Coordinator's Translation Endpoint is institutionalizing ELEGANT's coordination functions such that, by program end: the technology roadmap is industry-validated; ELEGANT-originated standards contributions are published or in formal ballot at SEMI, IEEE, or equivalent bodies; the IP framework is operating with executed licenses and a designated post-program administrator; and a successor structure with committed industry participation carries coordination functions forward without further NSF funding.

The Ecosystem Coordinator is responsible for the following program activities:

• Pollinator SMEs. Pollinators serve as the program's principal mechanism for sharing technical information across EPTs and Themes —monitoring technical results, identifying cross-cutting results and methods, and proactively communicating findings to applicable teams to eliminate redundant effort and prevent development silos. In their industry liaison role, Pollinators spend meaningful time embedded in industry partner organizations to understand what it would actually take to initiate a technology evaluation or qualification program for Low-D semiconductors, translating that intelligence back into technical recommendations to NSF to help ensure Expert Performer Team activities remain aligned to actual adoption requirements rather than assumed ones.

• Shepherd SMEs. Ensure EPTs maintain their execution schedules — tracking milestones, identifying and escalating risks and variances, and providing regular status reporting to NSF to help keep the program on track. Shepherds also help facilitate access to resources (e.g., fabrication access, characterization equipment, testbeds, computational or data resources, or other infrastructure). Shepherds provide this input throughout the period of performance, including at Go/No-Go decision points.

• Technology Roadmapping. Developing and maintaining an industry-informed and validated technology roadmap, submitted to NSF for approval and continuously updated based on EPT progress, ecosystem input, and monitoring of external global roadmapping activities. The roadmap is disseminated to EPTs and prospective industry adopters to help calibrate ongoing technical efforts against evolving industry needs and is also provided to the NSF to help inform national strategy for advancing U.S. leadership in Low-D semiconductor technology.

• Standards Development. Engaging SEMI, IEEE, and other standards bodies on behalf of ELEGANT— informed by EPT results, ecosystem input and monitoring of external standards activities— to advance Low-D semiconductor manufacturing, metrology, and qualification standards, and to help ensure U.S. leadership in international standards-setting for this technology class.

• Intellectual Property (IP) Framework Administration. Administering the ELEGANT IP Framework, including: tracking invention disclosures and coordinating patent filing activities; facilitating licensing and commercialization; monitoring compliance with the domestic commercialization preference and any foreign transfer restrictions; maintaining an ELEGANT IP registry; analysis and professional advice on IP-related issues; and reporting IP outcomes to NSF quarterly, including any identified compliance concerns related to foreign transfer, domestic manufacturing commitments, or unauthorized exceptions. The Ecosystem Coordinator has no authority to direct EPTs' IP decisions, approve/deny foreign transfers, or authorize manufacturing-location exceptions, which remain governed by each Team's OT Agreement and subject to NSF's approval.

• Industry Roundtable. Providing administrative support for the ELEGANT Industry Roundtable, including: scheduling and facilitating meetings; preparing materials summarizing EPT progress and ecosystem developments; and documenting Roundtable input for NSF's consideration.

Go/No-Go 1 (end of Phase 1) — Operational Readiness. Pollinator cross-team monitoring, information-sharing, and industry-intelligence-gathering processes, as well as Shepherd milestone, risk-tracking, and status-reporting processes, are fully staffed and operating at a highly effective level. Roadmap Version 1, incorporating the Theme 1 quality specification and interim results from Themes 2–5, is developed, validated through cross-theme input from EPTs and industry, and submitted to NSF. IP administration, the Industry Roundtable, and standards engagement are operational, and a coordination-effectiveness assessment has been conducted.

Go/No-Go 2 (end of Phase 2) — Demonstrated Value and External Traction. Roadmap version-2 industry-validated and Theme-specific progress tracks expectations set in roadmap; at least one formal standard work item opened at a recognized standards body (e.g., SEMI, IEEE) incorporating EPT technical content; industry adoption requirements are documented and, when accepted by NSF, translated into APP adjustments with implementation tracked; tangible IP facilitation results; and updated coordination-effectiveness assessment.

Go/No-Go 3 (end of Phase 3) — Institutionalization. Ecosystem Coordinator-facilitated industry engagements have matured into industry-initiated technology qualification activities;

Theme-specific progress meets or exceeds roadmap expectations with plans in place to realize future roadmap milestones; EPT-derived standards contributions published or advanced to formal industry ballot; ELEGANT IP Framework operating effectively, including any refinements / agreements necessary to support Phase 4 transition to industry funding.