DARPA-BAA-14-42_Amendment_2_CHIPS_Supplement_29_June_2015.pdf

DARPA-BAA-14-42

MTO Office-Wide BAA

Amendment Number 2 Common Heterogeneous Integration and IP reuse Strategies (CHIPS) for RF Electronics

Research Study

A. Funding Description

This amendment serves to supplement the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office Office-Wide BAA, DARPA-BAA-14-42. This research opportunity expands on the Globalization thrust described in Part II, Section I of the BAA and relates to the Heterogeneous Integration, Hardware for Advanced Signal Processing, Non-silicon Electronics, Microsystems for RF Transceivers, and Microsystem Design and CAD research topics identified therein. The DARPA Microsystems Technology Office seeks revolutionary ideas which address the increasing complexity of our major military systems and their inability to deal with rapid change by exploring new strategies for embracing global capabilities while maintaining trust, which will lead to affordable systems.

The DARPA Microsystems Technology Office is seeking innovative research (studies) for shortening electronics development time while vastly increasing performance and flexibility of RF electronic systems through a combination of intellectual property (IP) reuse and heterogeneous integration technology development. It is anticipated that successful solutions will enable large and massively complex systems with the ability to update underlying capabilities inexpensively and quickly. Such solutions will also allow for the quick adoption of new and modern electronics.

B. Background

The explosion of growth in mobile and telecommunication markets has pushed the semiconductor industry towards increased integration of digital, analog and mixed-signal blocks into system-on-chip (SoC) solutions. The exploitation of advanced silicon CMOS technology has enabled this integration but has also led to a rise in costs associated with design and processing. IP reuse has emerged as a tool to help lower design costs though it is primarily used in the digital domain for high volume designs. The complexity of advanced analog circuit design makes it risky to reuse analog intellectual property blocks. For both digital and analog designs, low volume design leads to high circuit development costs which disproportionately affect low-volume consumers such as the US Department of Defense (DoD). To enhance overall system flexibility and reduce design time, reusable design challenges in the digital and analog domains must be addressed.

At the hardware level, chip level integration has emerged as a primary strategy for increasing integration density in the silicon CMOS community, as the advancement of traditional transistor scaling has slowed. Both 2.5D and 3D integration flows currently exist for specific CMOS technologies, such as stacked memory, but these flows are typically proprietary and applicable to a limited set of process technologies. Also, the lack of a standardized integration interface limits the ability to reuse IP at the chip level. This situation slows realization of new circuit designs and adoption of new process technologies.

Beyond silicon CMOS electronics, long-term research in non-traditional platforms such as GaAs, InP, SiGe, and GaN have yielded distinct technological advantages. However, in many of these cases, it took over a decade to bring these discoveries from the lab to demonstrable products in the field. At the same time, the diffusion of technologies around the world has accelerated. Continued presence at the technological forefront will require a faster advanced technology adoption process that streamlines the identification and evaluation of promising technology and that shortens the ramp to integrating into the design toolbox.

C. Objective

The objective of the CHIPS RF Electronics Research Study is to explore solutions for increasing globalization in RF electronics by enabling IP reuse and seamless heterogeneous integration in analog mixed signal (AMS) designs. Research ideas that identify specific challenges to meeting these goals, describe possible solutions, and articulate how these solutions would be effectively implemented are of great interest. Technology demonstrations or design challenges that clearly illustrate feasibility are highly encouraged, when possible.

Both studies and demonstrations should quantify the benefits of the solution compared to state of the art or current best practices based on a meaningful set of metrics. Below are three technical areas of interest that are intended to serve as a guide.

D. Technical Areas of Interest

a. Technical Area 1 – IP reuse Ecosystem

Topics that discuss ways to enable IP reuse in AMS designs, such as setting up a comprehensive ecosystem, standardized IP block development, common toolsets and new IP management strategies, are of interest. Proposers are encouraged to motivate their research ideas with a convincing gap analysis of the issue they are addressing and provide clear goals with focused tasks.

Possible issues to consider include:

1) How would you enable the community to transition to your IP reuse strategy and maintain for reuse by the DoD community?

2) Describe quantitatively how parties would be incentivized to participate in this IP reuse model and what the anticipated savings in cost and time would be.

3) What are existing and needed standards to facilitate this IP reuse model?

4) Provide specific examples of design IP blocks that need to be developed in order to demonstrate this capability.

b. Technical Area 2 – Interconnect and Integration Technology

Methods that enable designers to choose the most optimal IP blocks for the intended application independent of process technology or material, as well as integration strategies to seamlessly combine these IP blocks, are of interest. Proposers are encouraged to motivate their research ideas with a convincing gap analysis of the issue they are addressing and to provide clear goals with focused tasks.

Possible issues to consider include:

1) What integration strategy is best suited to provide an advantage in performance and cost relative to conventional packaging techniques and how would one justify this choice over another?

2) What development is required to realize this integration strategy?

3) How will compatibility be ensured among multiple vendors (e.g. standards based)?

4) Propose possible design challenges that demonstrate a viable interconnect or integration strategy for heterogeneous AMS blocks.

c. Technical Area 3 – New Process Technologies

Technical area 3 seeks research ideas on new process modules to augment an IP reuse ecosystem and enable it to continue to evolve. Solutions may include rationale for new process technology investment, such as a tradeoff analysis of relevant metrics (e.g.

performance, cost, production, integration, and the time it takes to bring new technology online), the methodology for introducing targeted new process modules into the toolbox, and the application strategy for the new set of process modules. Proposers are encouraged to motivate their research ideas with a convincing gap analysis of the issue they are addressing and provide clear goals with focused tasks.

Possible issues to consider include:

1) What is the new process and what are its differential advantages relative to released processes?

2) What infrastructure is needed to develop, test and deploy this process module?

3) How would the new process module accommodate a standards-based interconnect strategy?

4) How would the new process technology demonstrate its advantages on key benchmarks and a feasible integration strategy?

E. Proposal Submission Instructions

The suggested duration and cost of potential efforts is less than 12 months in length and on the order of $500,000 or less, respectively. Proposers are also encouraged to include a clear list of deliverables with both near-term (3-4 months) and longer-term deliverables.

CHIPS RF Electronics Research Study proposals should be prepared and submitted in accordance with the guidance provided in DARPA-BAA-14-42 (MTO Office-Wide BAA). It is requested that CHIPS RF Electronics Research Study proposals be received by no later than July 29, 2015 (2:00pm EST), however proposals received prior to the due date/time specified in DARPA-BAA-14-42 will be reviewed.