Specs_rev..pdf

Addendum: DVB-S2X Demodulator Intellectual

Property FPGA Implementation & License

1 OVERVIEW

The NASA Glenn Research Center also requires a DVB-S2/S2X-compliant demodulator intellectual property FPGA implementation and license for a ground demonstration of Ka-band communications through a LEO/MEO/GEO relay satellite. This purchase will be deliverable electronically as an implementable computer coded-design compatible with Xilinx Vivado Design Suite tools. The demodulator will be used initially in a laboratory setting for the development of a compatible waveform for a custom software-defined radio implementation.

2 MINIMUM SPECIFICATIONS

2.1 APPLICABLE STANDARDS

The DVB-S2X demodulator design shall be compliant with the DVB-S2/S2X standards, ETSI EN 302 307-1 and ETSI EN 302 307-2 respectively.

2.2 FEATURES

The DVB-S2X demodulator shall support the following features in the table below:

Parameter Minimum Specification

Input Interface Complex baseband digital samples

Output Symbol Rate Variable and configurable, must support 100 Mbaud channel symbol rate on a single Xilinx XQ7K410TRF900-1M FPGA with device utilization <25%

Modulation types Support for QPSK to 256-APSK. Include all constellations per ETSI EN 302 307-1 and ETSI EN 302 307-2

Filter Roll-off Factors 5%, 10%, 15%, 20%, 25% to 35%

Physical Layer (PL) Framing Features

PL frame recovery and deframing, both with and without pilot symbol insertion

Frames sizes Short (16,200 bits) and Normal (64,800 bits)

Implementation Loss <1.0dB relative to quasi-error-free performance specified in ETSI standards

Mode Support Constant Coding and Modulation (CCM) Variable Coding and Modulation (VCM) Support for Adaptive Coding and Modulation (ACM)

Support Code Test bench and simulation code, preferably compatible with Vivado Simulator

Software Model MATLAB, C/C++, or other bit-accurate model

2.3 DELIVERY FORMAT

Designs should be delivered as an encrypted RTL source (preferred) or netlist.

2.4 LICENSE TERMS

Single project use. Deployed on up to three (3) development units including Xilinx 7-series and/or

Ultrascale parts.

2.5 DELIVERY

Electronic delivery of IP design 30 days after receipt of order.