Government_requirement.pdf

Government Requirements

Highly Uniform Device Layer Thickness Silicon-on-Insulator Wafers

Background:

The National Institute of Standards and Technology’s, Nanomechanical Properties Group of the Materials Measurement Science Division is developing a Reference Material (RM) for calibrating optical profilometry tools and 3D microscopes. This RM requires precise and accurate control over all three dimensions of the artifact being produced by microfabrication of a custom Silicon-on-Insulator (SOI) wafer stack. To achieve the accuracy and precision required in the z-direction, the thickness uniformity of device layers of the SOI wafers used to build the artifact must be better than 2%.

Silicon-on-Insulator (SOI) wafers are commercially available from many vendors and are produced using several methods including bond and grind, SiMOX, and SmartCut. Of these three processes, SmartCut produces thin device layers (< 2µm) with very uniform thickness (< 2% at 6σ). Other processes (e.g. bond and grind—the most common SOI production method) have thickness uniformities larger than 25% at 4σ. Since the RM being developed is a step height standard and device layer thickness dictates the step height, highly uniform device layer thickness is a technical requirement.

Specifications:

• Stack

- Diameter: 200 mm conforming to SEMI specifications including notch position

- Quantity: 20 each o Total Thickness Variation (TTV): < 10 µm o Edge Exclusion: ≤ 5 mm

• Device Layer o Thickness Uniformity: better than ±2% at 6σ o Thickness: between 1400 nm and 2000 nm, 1500 nm is preferred o Crystal Orientation: (100) Si ± 1° o Conductivity & Dopant: no requirement

• Buried Oxide Layer (BOX) o Thickness: between 190 nm and 310 nm

• Handle Layer o Thickness: between 480 µm and 775 µm o Crystal Orientation: (100) Si ± 1° o Notch/Flat: <110> ± 0.5° per SEMI standard o Conductivity: >0.01 Ω∙cm o Dopant: no requirement

Delivery Date: within 8 weeks after receipt of order