Project Grant 2628056

I-CORPS: TRANSLATION POTENTIAL OF VERIFIABLE REWARD-SIGNAL GENERATORS FOR AGENTIC REINFORCEMENT LEARNING (RL) ENVIRONMENTS -THIS I-CORPS PROJECT IS BASED ON THE DEVELOPMENT OF A SOFTWARE PLATFORM THAT GENERATES FEEDBACK FOR TRAINING AND EVALUATING ARTIFICIAL INTELLIGENCE (AI) SYSTEMS. AS AI IS INCREASINGLY TRAINED TO ACT ON ITS OWN THROUGH TRIAL AND ERROR, THE CENTRAL BOTTLENECK IS EVALUATING A SYSTEM FOR CORRECTNESS. CURRENTLY, THIS DEPENDS ON COSTLY HUMAN REVIEW OR ON HAND-BUILT CHECKS THAT AUTOMATED SYSTEMS LEARN TO EXPLOIT RATHER THAN SATISFY, SLOWING PROGRESS ACROSS AN INDUSTRY NOW INVESTING TENS OF BILLIONS OF DOLLARS ANNUALLY. THIS TECHNOLOGY IS DESIGNED TO GENERATE PRECISE, MACHINE-CHECKABLE FEEDBACK SIGNALS AT VERY LOW COST, ALLOWING DEVELOPERS TO TRAIN AND MEASURE AI AGAINST VERIFIABLE STANDARDS RATHER THAN APPROXIMATIONS. THIS APPLIES TO MOST USES OF AI INCLUDING SOFTWARE DEVELOPMENT, COMPUTER CHIP DESIGN, CYBERSECURITY, AND SCIENTIFIC COMPUTING. THIS MAY MAKE MACHINE BEHAVIOR EASIER TO MEASURE AND SUPPORT A SAFER, MORE TRANSPARENT, AND MORE COMPETITIVE TECHNOLOGY ECONOMY. THIS I-CORPS PROJECT UTILIZES EXPERIENTIAL LEARNING COUPLED WITH FIRST-HAND INVESTIGATION OF THE INDUSTRY ECOSYSTEM TO ASSESS THE TRANSLATION POTENTIAL OF A PLATFORM FOR REINFORCEMENT LEARNING FROM VERIFIABLE REWARDS (RLVR) THAT GENERATES CORRECTNESS FEEDBACK AT NEAR-ZERO MARGINAL COST. THE CORE TECHNOLOGY COMBINES FORMAL METHODS, INCLUDING TEMPORAL LOGIC SPECIFICATION, AUTOMATED SYNTHESIS, AND SATISFIABILITY CHECKING, WITH PHYSICAL COMPUTE SUBSTRATES, PRINCIPALLY FIELD-PROGRAMMABLE GATE ARRAYS (FPGAS), TO EVALUATE MACHINE BEHAVIOR AGAINST MATHEMATICALLY DEFINED CORRECTNESS CRITERIA. UNLIKE CONVENTIONAL REWARD DESIGN, WHICH RELIES ON HEURISTIC SCORING OR HUMAN LABELING THAT AGENTS CAN GAME, THIS APPROACH DERIVES FEEDBACK FROM FORMAL GUARANTEES, PRODUCING SIGNALS THAT ARE PRECISE, REPRODUCIBLE, AND RESISTANT TO EXPLOITATION. CERTAIN REWARD DIMENSIONS, INCLUDING REAL CONTENTION THROUGHPUT, HARDWARE SIDE-CHANNEL BEHAVIOR, AND DEVICE-LEVEL PROCESS VARIATION, ARE PHYSICALLY IRREDUCIBLE AND CANNOT BE FAITHFULLY SIMULATED, MOTIVATING EXECUTION ON PHYSICAL FPGA FABRIC. DEMONSTRATED PROOF-OF-CONCEPT INSTANCES INCLUDE BENCHMARK ENVIRONMENTS FOR TEMPORAL-LOGIC REASONING AND HIGH-THROUGHPUT SATISFIABILITY SOLVING, WHERE VERIFIABLE REWARDS ARE PRODUCED AUTOMATICALLY AND AT SCALE. DEVELOPERS TRAINING AUTONOMOUS AGENTS, EVALUATING HARDWARE DESIGN TOOLS, AND STRESS-TESTING SYSTEM SECURITY MAY BENEFIT FROM FEEDBACK THAT IS CHEAPER AND FASTER THAN CURRENT PRACTICE. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE NOT PLANNED FOR THIS AWARD.