Sbir phase i: efficient arithmetic on quasi-compressed data for performance improvement

This $256,000 National Science Foundation project grant funds the development of an arithmetic and math hardware accelerator capable of processing compressed floating-point data by Arith Inc. The accelerator aims to dramatically improve computation performance, storage effectiveness, and energy efficiency for computationally intensive applications by enabling arithmetic operations directly on compressed data, rather than requiring decompression first as with current computer systems. Specifically, the award supports Arith Inc. in developing the first-ever compressed floating-point unit that minimizes semiconductor and energy usage and reduces computation latency. The project is aligned with the NSF Directorate for Engineering's goal of fostering innovation in engineering research to improve quality of life and economic strength through support of projects developing novel engineering solutions.

Abstract

The broader impact of this small business innovation research (sbir) phase i project is to improve the performance of semiconductor chips. Specifically, IT develops a novel method to operate directly on compressed data, saving time, energy, and latency. This improved performance will affect computationally intensive applications such as medical imaging (e.g., CT/MRI), climate simulation, hurricane warnings, and earthquake alerts. This small business innovation research (sbir) phase i project develops a method to operate on compressed data. Today, computers apply data compression to identify and remove redundancy in the data in order to save storage space. Computers apply arithmetic to compute in integers or real numbers (usually represented internally as floating-point data). However, today's computers first decompress the data, compute, and then compress the computed result, consuming additional time and energy. This project develops an arithmetic and math hardware accelerator capable of processing compressed data directly to dramatically improve computation performance, storage effectiveness, and energy efficiency. This project combines data compression and floating-point engineering to deliver the first-ever compressed floating-point unit (cfpu) that minimizes semiconductor and energy usage and reduces computation latency. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the foundation's intellectual merit and broader impacts review criteria.