PURPOSE: THE PURPOSE OF THIS WORK IS TO DEVELOP ACCURATE CRYOGENIC COMPACT MODELS FOR SHORT-CHANNEL CMOS TRANSISTORS SPECIFICALLY 28NM BULK AND 16NM FINFET TECHNOLOGIES USING EMPIRICAL DATA COLLECTED BY NIST AND ITS UNIVERSITY COLLABORATORS. THESE MODELS WILL ENABLE PREDICTIVE CIRCUIT SIMULATION AND FIRST-PASS DESIGN SUCCESS FOR CRYOGENIC INTEGRATED CIRCUITS, SUPPORTING NISTS EFFORTS IN ADVANCING QUANTUM COMPUTING AND OTHER LOW-TEMPERATURE APPLICATIONS. ACTIVITIES TO BE PERFORMED: THE PROJECT WILL INVOLVE EXTRACTING COMPACT MODEL PARAMETERS FOR 28NM BULK AND 16NM FINFET TRANSISTORS USING CRYOGENIC MEASUREMENT DATA. EXISTING MODELS WILL BE CALIBRATED TO REFLECT LOW-TEMPERATURE BEHAVIOR AND VALIDATED AGAINST EXPERIMENTAL RESULTS. THE FINALIZED MODELS WILL BE DOCUMENTED FOR USE IN CIRCUIT SIMULATION TOOLS, AND REPRESENTATIVE CRYOGENIC CIRCUITS WILL BE SIMULATED TO DEMONSTRATE MODEL APPLICABILITY. RESULTS WILL BE SHARED THROUGH TECHNICAL REPORTS AND PUBLICATIONSEXPECTED OUTCOMES: THIS PROJECT WILL DELIVER VALIDATED CRYOGENIC COMPACT MODELS FOR 28NM BULK AND 16NM FINFET TRANSISTORS, ENABLING ACCURATE CIRCUIT SIMULATIONS AT TEMPERATURES DOWN TO 4K. THESE MODELS WILL SUPPORT FIRST-PASS DESIGN SUCCESS FOR CRYOGENIC CIRCUITS AND CONTRIBUTE TO THE BROADER CRYO-CMOS DESIGN INFRASTRUCTURE.INTENDED BENEFICIARIES: THIS WORK WILL BENEFIT CIRCUIT DESIGNERS, RESEARCHERS, AND SYSTEM DEVELOPERS WORKING IN QUANTUM COMPUTING AND ADVANCED CRYOGENIC ELECTRONICS BY PROVIDING ACCURATE COMPACT MODELS FOR SHORT-CHANNEL TRANSISTORS AT LOW TEMPERATURES. THESE MODELS WILL HELP CLOSE THE CURRENT CRYO-CMOS DESIGN CAPABILITY GAP, ENABLING MORE RELIABLE AND EFFICIENT SIMULATION-DRIVEN CIRCUIT DESIGN IN EMERGING CRYOGENIC APPLICATIONS.SUBRECIPIENT ACTIVITIES: THE RECIPIENT DOES NOT INTEND TO SUBAWARD FUNDS.