Sbir phase II: low-cost packaging solution for space-grade and high-reliability integrated circuits

The National Science Foundation (NSF) awarded a $999,561 Cooperative Agreement under its Technology, Innovation, and Partnerships (CFDA 47.084) program to Apogee Semiconductor, Inc. to develop a cost-effective and reduced-size packaging solution for space-grade and high-reliability integrated circuits. The project aims to redesign the redistribution layer within wafer-level chip-scale packaging (WLCSP) to improve reliability under the extreme temperature cycling experienced in space applications. By compensating for the thermal expansion mismatch between silicon die and the copper circuit board, this innovation will enable the benefits of WLCSP, such as smaller size and weight, to be more widely accessed by the space industry. Apogee Semiconductor plans to collaborate with subawardees on this 2-year effort, which commenced on December 1, 2023.

Abstract

This small business innovation research (sbir) phase II project enables the use of modern packaging technologies for integrated circuits in space applications. While failures in satellites are common and high insurance claims due to such failures are frequent, the space industry continues to use integrated circuits (ICS) that are either unreliable (non-space-grade) and are prone to failure, or space-grade ICS with large and costly packaging and compromised performance. This innovation offers a cost-effective and reduced-size solution for the packaging of ICS that can operate reliably over the extreme temperature cycles experienced in space applications. Wafer level chip scale packaging (wlcsp) is lighter, smaller, and has superior electrical and thermal performance when compared to traditional leaded packaging solutions. These attributes make IT desirable to the space industry by reducing size and weight, while not compromising performance. As this packaging technology is limited due to its performance under temperature cycling, this project seeks to address this reliability problem by using existing manufacturing techniques coupled with a novel design concept. This small business innovation research (sbir) phase II project aims to redesign specific layers within the existing wafer level chip scale packaging (wlcsp) to improve reliability under temperature cycling. The temperature cycle reliability problem in the wlcsp is caused by a thermal expansion rate mismatch of silicon DIE and the copper circuit board. This project will redesign the redistribution layer within the wlcsp to compensate for this mismatch by effectively moving the interconnects on the silicon DIE in accordance with the faster moving printed circuit board (PCB). This project will make the benefits of wlcsp accessible for the entire space community. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the foundation's intellectual merit and broader impacts review criteria.- subawards are planned for this award.