A novel data processing accelerator intellectual property (IP) radiation-hardened-by-design (RHBD) core for use in NASA future missions is proposed. The core is an artificial neural network…

This is a firm-fixed-price contract awarded by the National Aeronautics and Space Administration (NASA) Shared Services Center to Microelectronics Research Development Corporation (MRDC), a for-profit organization, under the Small Business Innovation Research (SBIR) Program Phase I. The contract is for the development of a radiation-hardened-by-design (RHBD) tensor core, which is an artificial neural network accelerator, to be used in future NASA missions. The tensor core is designed to be compliant with the Advanced Microcontroller Bus Architecture (AMBA) and will feature an expandable architecture to accommodate increased processing requirements. The $124,931 contract is intended to help decrease the downlink data bandwidth needed for future space missions by enabling more in-situ data processing. The tensor core will also be incorporated into MRDC's future Reticle Programmable System on Chip (RPSoC) platform, which is under development with NASA and Air Force funding to enable lower-cost and faster development of digital and mixed-signal designs at the 32nm process node.

A novel data processing accelerator intellectual property (IP) radiation-hardened-by-design (RHBD) core for use in NASA future missions is proposed. The core is an artificial neural network accelerator based upon work done at google, IBM, and others. The IP core is known as a tensor core and follows an architecture of matrix multipliers, accumulators, register files, and fast and abundant memory access. The tensor core will be developed to be advanced microcontroller bus architecture (AMBA) bus compliant and will feature an architectural approach to easily expand the data processing elements when more DIE area is available. The core will be developed on the trusted global foundries (GF) 32NM silicon on insulator (SOI) process. There is extensive development currently occurring at this process technology, including NASA S future high performance spaceflight computing (HPSC) platform. The core is proposed as an effort to develop a data processing acceleration to decrease the down-link data bandwidth of future space missions. If more processing can be accomplished in situ, a given mission can be expected to require less data bandwidth, a problem that is becoming more critical with the ever increasing number of active missions. The IP core will be developed to be incorporated into other development at the 32NM process. The IP core will also be structured in such a way as to be incorporated into micro-RDC S future reticle programmable system on chip (RPSOC) platform. The RPSOC is an active future platform, under development with funding from NASA and the air force, for digital and mixed signal designs to lower the cost of development at 32NM and to decrease lead-time from design inception to product delivery. The tensor core will be featured on this platform as a data acceleration core. The core will have RHBD techniques throughout the feol and beol to ensure that no data will be corrupted within the artificial neural network configuration or the data path.