One of the key components in many NASA missions is a large-format focal plane focal plane array (FPA) to capture images or two-dimensional, hyperspectral information, especially in the infra-red…

This is a Small Business Innovation Research (SBIR) Phase II contract awarded by the National Aeronautics and Space Administration (NASA) to Sensor Creations, Inc., a Subchapter S Corporation, to develop a novel read-out integrated circuit (ROIC) with individual pixel programmability for astronomy infrared focal plane arrays. The total potential value of the contract is $749,177.00. The key deliverable is a ROIC design that addresses limitations in image persistence and inter-pixel capacitance, enabling improved performance for infrared focal plane arrays used in many NASA missions. This contract builds on the work conducted in the previous SBIR Phase I, where the company completed the initial design and simulation of the ROIC architecture.

One of the key components in many NASA missions is a large-format focal plane focal plane array (FPA) to capture images or two-dimensional, hyperspectral information, especially in the infra-red (IR) domain. Apart from the detector, the performance of these fpas is determined by the read-out integrated circuit (ROIC) that amplifies and multiplexes photo generated charge for signal processing by peripheral circuitry. In this project, we propose to develop a new ROIC for low background applications, specifically designed to overcome present limitations of image persistence and inter-pixel capacitance (IPC). The main innovation in this project is an adaptive unit cell that can be individually and randomly programmed via on-chip logic to control bias state and reset duration of any pixel in the array while the integration of science data is on-going. In phase I we conducted a pixel trade study and performance evaluation for a capacitive trans-impedance amplifier (CTIA) and a source follower per detector (SFD) type pixel using analog circuit simulations. Then we generated the optimum unit cell layout, defined the overall architecture and created the top-level schematic. By the end of phase I we have completed the blue prints for the design. The completion of the top-level schematics, verified through simulation, is a critical milestone in the development. IT substantially reduces the risk associated with creating new ROIC technology and will allow US to efficiently fabricate and test the device in phase II. All results from phase I are documented in a preliminary interface control document (ICD) so that the new ROIC can be considered for future missions. In phase II we will produce the layout of the entire chip for fabrication using stitching lithography in a state of the art cmos foundry and demonstrate its functionality on packaged prototypes. By the end of phase II, wafers of a known functioning ROIC design will be available for hybridization.