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PD10WRGBGBEA34, Rev E
CAGE 98752
13 January 2012
Logic 1 and 0 shall be individually, independently programmed. I/O channels shall be programmable in input voltage, output voltage, output current and single/differential mode in groups of 8 or less. Channels shall be programmable as input or output in sub-groups of 4 or less. The LV and HV parallel channels shall be individually programmable in output voltage amplitude on each channel within the voltage ranges specified in Table 3-18. Two level sets shall be provided per 16-channel group. Each parallel controller’s internal clock shall be externally available at the ICA. A strobe signal shall be available at the ICA indicating when input data is transmitted to the UUT. At a minimum, each parallel bus controller shall have an externally provided start, gate and sync input at the ICA. Each signal source shall comply with the requirements listed below and in Table 3-18. All specified parameters shall be verified at the ICA.
LV Parallel I/O (Quantity of 216)
| +5 Volt Discretes |
| Differential Voltage Range |
| 0 to +5 V |
| Voltage Accuracy |
| ± 0.1 VDC |
| Programmable Resolution |
| 100 mV |
| Rise and Fall Time |
| 50 ns Max |
| Repetition Rate |
| DC to 200 Hz |
| ±5 Volt Discretes |
| Voltage Range |
| -5V to +5V |
| Programmable Resolution |
| 100 mV |
| Rise and Fall Time |
| 500 ns Max |
| Repetition Rate |
| DC to 200 Hz |
| ±12 Volt Discretes |
| Voltage Range |
| -12V to +12V |
| Programmable Resolution |
| 250 mV |
| Rise And Fall Time |
| 50 ns Max |
| Repetition Rate |
| DC To 200 Hz |
HV Parallel I/O (Quantity of 24)
| ±30 Volt Discretes |
| Voltage Range |
| - 31V to + 31V |
| Programmable Resolution |
| 100 mV (0-5V), 500 mV (>5V) |
| Current |
| 50 mA nominal, 250 mA max |
| Rise And Fall Time |
| 500 ns Max |
| Repetition Rate |
| DC To 200 Hz |
Table 3-18, Parallel I/O Signals