PD10WRGBGBEA34 rev A_R3.pdf

PD10WRGBGBEA34 rev A

CAGE 98752

30 November 2010/R3

Beneficial comments, recommendations, additions, deletions, clarifications, etc. and any data that may improve this document should be sent to: WR-ALC/GRNEA, Robins

AFB, GA 31098-1611

Distribution Statement A. Approved for public release; distribution is unlimited. FSC 4920

PURCHASE DESCRIPTION (PD)

Advanced Radar/Electronic Warfare Test Station (ARTS)

1.0 SCOPE

1.1 Scope. This document details system requirements for the performance of the Advanced Radar/Electronic Warfare Test Station (ARTS) and associated Test Program Sets (TPSs). The ARTS is intended to replace the functionality of the following legacy test systems in support of testing and repairing of Line Replaceable Units (LRUs) in the AN/ALQ-161A subsystem on the B-1B: Radar/Electronic Warfare (REW) test station, Radio Frequency (RF) Defense Automatic Test Equipment (ATE) Augmentation Equipment (DAAE), and the Digital DAAE. The ARTS will be considered as one integrated unit to replace the current functionality of these three (3) legacy ATE systems for testing the LRUs listed in Table 2-1.

2.0 APPLICABLE DOCUMENTS

2.1 Non-government documents.

IEEE Std 1671 IEEE Trial-Use Standard for Automatic Test Markup Language (ATML) for Exchanging Automatic Test Equipment and Test Information via XML

IEEE Std 1636 IEEE Trial-Use Standard for Software Interface for Maintenance Information Collection and Analysis

(SIMICA)

VXI-1, Rev 3.0 VXIbus System Specification PXI-1 Rev 2.2 PXI Hardware Specification PXI-2 Rev 2.3 PXI Software Specification PXI-5 Rev 2.0 PXIexpress Hardware Specification PXI-6 Rev 1.1 PXIexpress Software Specification IEEE Std 488.2 – 1992 Standard Digital Interface for Programmable

Instrumentation IEEE Std 802.3 – 2008 Standard for Information technology-Specific requirements - Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications

PD10WRGBGBEA34

2.2 Government Documents.

2.2.1 Specifications, Standards and Handbooks. The following specifications, standards, and handbooks form a part of this document to the extent specified herein.

However, a later affectivity may be used if it does not degrade from the affectivity of the specification stated herein. In the event of a conflict between this document and documents stated herein, the precedence established in 2.3 shall apply.

AFI 33-202 Change to Communications and Information Specialized Publications

AFOSH STD 48-9 Radio Frequency Radiation (RFR) Safety Program AFOSH STD 48-20 Occupational Noise and Hearing Conservation

Program AFOSH STD 48-139 Laser Radiation Protection Program

AFOSH STD 91-10 Civil Engineering AFOSH STD 91-25 Confined Spaces

NFPA 70 National Electric Code AFOSH STD 91-501 Air Force Consolidated Occupational Safety Standard AFSSI 8580 Remanence Security MIL-PRF-15733H Filters And Capacitors, Radio Frequency Interference, General Specification For MIL-HDBK-454B General Guidelines For Electronic Equipment MIL-PRF-28800F Test Equipment For Use With Electrical And

Electronic Equipment, General Specification For MIL-STD-129P Military Marking for Shipment and Storage MIL-STD-209K Lifting and Tie-Down Provisions MIL-STD-1332B Definitions Of Tactical, Prime, Precise, And Utility

Terminologies For Classification Of The DOD Mobile Electric Power Engine Generator Set Family

MIL-STD-1472F Human Engineering MIL-STD-1839D Calibration And Measurement Requirements, Standard Practice For MIL-STD-2073-1E Military Packaging, Standard Practice for MIL-STD-130N Identification Marking of U.S. Military Property FED-STD-595C Colors Used in Government Procurement MIL-STD-882D System Safety MIL-STD-1553B Digital Time Division Command/Response Multiplex

Data Bus MIL-STD-461F Requirements for the Control of Electromagnetic

Interference Characteristics of Subsystems and Equipment

L409C2011 B-1 Air Vehicle Standard Signal Interface, General Specification For

A-A-59828 Commercial Item Description (CID), Oil Cooling Cart MIL-STD-810 Test Method Standard for Environmental Engineering

Considerations and Laboratory Tests

2.2.2 Applicable LRUs

LRU NAME NSN PART NO.

TWF R/P (RP) 5865-01-551-7118 435097-6

BAND 8 RFS 5865-01-553-2000 435029-12

JAMMER LOGIC B (JLB) 5865-01-545-4411 442600-6

JAMMER LOGIC A (JLA) 5865-01-545-2484 442590-6

BAND 7 RFS 5865-01-257-2789 442001-3

BAND 6 RFS 5865-01-257-1341 442000-3

ENCODER 5865-01-264-3364 440314-4

GENERATOR, REFERENCE

SIGNAL (WAVEFORM

GENERATOR, WFG-8)

5895-01-497-7220 435030-7

DF ENCODER (DFE) 5868-01-516-0698 0065001-7

BAND 5 AFT TX (TX5A) 5865-01-331-2557 435098-6

BAND 6 TX (TX6) 5865-01-362-6438 001-006822-011

BAND 7 TX (TX7) 5865-01-240-3754 001-006824-006

RX BANDS 4-8 5865-01-256-2544 435019-5

FREQ CHANNELIZER (FCH) 5895-01-239-8983 447719-1

CONT INTERFACE UNIT (CIU) 5865-01-258-1148 442654-4

BAND 6 DRIVER (DR6) 5865-01-240-3755 001-006821-006

BAND 7 DRIVER (DR7) 5895-01-240-0091 001-006823-006

ADVANCED TRACKING UNIT

(ATU)

5865-01-257-1244 442655-4

RX THRESHOLD CONTROL

(RTC)

5865-01-258-7062 435034-5

LRU NAME NSN PART NO.

BANDS 4/5 RFS 5865-01-258-1133 435026-8

RECEIVER, COUNTERMEASURE

(IR-5)

5865-01-454-0015 440313-5

BAND 8 DRIVER/TX (DR/TX8) 5865-01-240-0092 001-006812-011

BAND 5 FWD 5865-01-257-2861 435025-4

BAND 4 FWD TX 5865-01-256-6556 435023-4

BAND 4 AFT TX 5865-01-258-7063 435024-7

BAND 7 ADR (ADR7) 5821-01-239-9984 0062001-3

BAND 6 TX ANT AFT (TA6A) 5985-01-217-7376 0072001-2

RX BANDS 1-3 5865-01-258-7061 435018-6

BAND 8 TX ANT AFT (TA8A) 5985-01-240-8402 0077001-2

BAND 8 TX ANT FWD (TA8F) 5985-01-240-3271 0078001-5

BANDS 6/7/8 ADR (ADR6-8) 5985-01-240-4224 0064001-6

BAND 6 TX ANT FWD (TA6F) 5985-01-217-7425 0073001-2

BAND 6 ADR (ADR6) 5985-01-238-7922 0061001-2

BAND 7 TX ANT (TA7) 5985-01-335-4937 0074002-3

BAND 8 ADR (ADR8) 5985-01-240-4223 0063001-3

Table 2-1 Applicable LRUs

2.3 Order of Precedence. In the event of a conflict between the text of this PD and the references cited herein (except those pertaining to LRU testing requirements and/or specifications) the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.

3.0 REQUIREMENTS

Equipment covered by this PD may be commercially available equipment modified to the extent necessary to meet the following description. The equipment shall be Class 3 in accordance with MIL-PRF-28800 except as specified herein.

3.1 General Design. The ARTS shall, as a minimum, facilitate performing the following tasks, but not to be limited to:

a. Testing each LRU in Table 2-1 including fault isolation to the faulty shop replaceable unit (SRU) or subassembly.

b. Installing and removing SRU(s).

c. Removing and installing major assemblies.

d. Providing the required tools and technical data for fault isolation to the SRU level. These tools could be extender cards, probes, and common test equipment.

e. Providing stimulus and measurement for LRU testing without requiring external instrumentation.

f. Providing the capability to collect, store, and export testing data for analysis.

g. Providing storage for tools, cables, handbooks, operating and servicing instructions, ensuring retention of these items during transport and providing appropriate environmental protection.

3.1.1 Commerciality. The ARTS shall be based on an open architecture design in allowing for the maximum implementation of COTS equipment. The contractor shall use commercial parts, components, and items to the maximum extent practicable in the production of the ARTS, and shall strive to minimize the size and weight of the overall system without adversely affecting performance. Synthetic Instrumentation (SI) and/or instrument-on-a-card, such as PXI (or PXI Express) and VXI, shall be used to the maximum extent possible to minimize the physical size and logistics footprint of the station. The ARTS shall include the use of a minimum of two (2) SI chassis for implementation of instrumentation to meet the performance requirements of section 3.2.

This minimum of 2 chassis shall be 2 PXI chassis, 2 VXI chassis, or a combination of 1 PXI chassis and 1 VXI chassis.

3.1.2 Markings. All external devices which require an operational or maintenance interface shall be marked in accordance with MIL-STD-130. Painted markings shall be 1-inch high block letters unless prohibited by the available space. In such cases the markings shall be the largest size possible but shall not be less than 1/2-inch high.

Markings, Information/Caution shall be Lusterless Black Color Number 37038 of FED-

STD-595 and Markings, Warning/Danger shall be Lusterless Red Color Number 31136 of FED-STD-595.

3.1.3 ID Plate. An identification Plate in accordance with MIL-STD-130 shall be securely attached to the ARTS in a readily accessible location. The identification plate shall contain the following information: nomenclature, model or part number, serial number, contract number, gross station weight, manufacturer's name and Commercial and Government Entity (CAGE) code, National Stock Number (NSN), and Item Universal Identification (IUID). IUID information shall be included as both a bar code and legible markings.

3.1.4 Mobility. Although there is no requirement for transportability or deployment of the test station, the station shall be designed with caster jacks or other means to enable easy movement of the station while completely assembled within an environmentally controlled maintenance shop. The caster jacks shall have brakes to secure the station in place when not in movement. The primary purpose of this mobility requirement is for relocation of the station within the maintenance shop and access to rear of station for maintenance actions.

3.1.5 Jack Access. ARTS shall be slotted and modular to the extent required to enable movement by a forklift truck rated for lifting 4000 pounds (max).

3.1.6 Materials, Processes, and Parts. Materials, processes and parts for the ARTS equipment shall be in accordance with contractor / industry published best commercial practices and MIL-PRF-28800.

3.1.7 Grounding. A controlled grounding concept shall be used so that grounding will not adversely impact the functional testing/operation of the Unit Under Test (UUT). This concept shall provide for a single point ATE signal ground as well as a single point safety ground.

The ARTS enclosures shall be designed to permit a safety ground connection to facility ground. An external ground stud shall be provided for this purpose. The structural components of the equipment (consoles, rack, test stands, etc.) shall be connected to this safety ground connection and each path shall be capable of carrying that component's fault power current. The maximum resistance between any two bonded adjacent assemblies shall be less than 25 milliohms. A safety ground stud shall also be provided on the front of the ARTS for the operator to use in grounding himself or the equipment for safety and electrostatic discharge (ESD) protection.

Power input neutrals shall not be grounded within the station. The signal and safety grounds shall be DC isolated from the primary input power returns by a least 1 megohm and shall be brought out of the equipment on separate connector pins or connections.

3.1.8 Workmanship. Workmanship of the ARTS equipment shall be consistent with the requirements specified herein. There shall be no imperfections that could reasonably be expected to prevent the requirements of this specification from being met. There shall be no evidence of detrimental sharp corners or edges, cracks, blemishes, cuts, gouges, defects, burrs, and displaced or missing parts. Fastening, clamping, supporting, and locking devices shall be correctly installed without damage. There shall be no detrimental foreign matter internally or externally.

3.1.9 Interchangeability. ARTS assemblies and subassemblies shall be designed for interchangeability between the same ATE configurations. Consideration shall be given to interchangeability of components, assemblies and subassemblies to minimize sparing, simplify design, and reduce overall costs. Standard parts and assemblies shall be used when available, practical and cost-effective.

3.1.10 Safety. The ARTS shall be designed to eliminate or control safety hazards using MIL-STD-882, MIL-STD-1472 para. 5 through 5.13 and MIL-PRF-28800 para. 3.2 as a guide. This shall include, but not be limited to the following safety considerations:

Warning labels on areas where high voltage is present.

Emergency power interrupt switch readily accessible to the operator.

Over voltage and over current protection on power supplies.

Over temperature sensors and shut-down. Provide notification to operator for

“regular” over temperature condition. Provide notification and automatic orderly power shutdown for “critical” over temperature condition.

Mechanisms to prevent equipment tip-over when drawers are extended or Interface Test Adapters (ITAs) are installed.

Safety stops on drawer-slides.

Protective guards on cooling fans.

Rounded corners on exposed edges.

Safety ground straps on all enclosures and connection point to facility ground.

ESD warning labels to identify circuitry sensitive to static damage.

The design of the test station shall not contain any system safety mishap risk categories greater than medium as defined in Table A-IV of MIL-STD-882.

3.1.11 Human Performance/Human Engineering. MIL-STD-1472 shall be used for human engineering design. The human engineering objectives are to ensure satisfactory performance of tasks, simplify operator functions, minimize the probability of human error, and reduce the skill and training requirements.

3.1.12 Acoustical Noise. The maximum sound level produced by the ARTS, as measured at the operator’s normal work station, shall not exceed 70 dBA.

3.2 Performance Requirements. The following subsections contain the minimum system-level performance requirements of the ARTS. The functional allocation and design specifications shall be derived by the supplier via analysis of the testing requirements of the LRUs listed in Table 2-1 and the requirements of this PD.

Consolidation of functional requirements and design specifications contained in these subsections is acceptable while still meeting the testing requirements of the LRUs listed in Table 2-1.

The ARTS shall be capable of providing the following stimuli to the UUTs and receiving/measuring the following response signals from the UUTs. All specified parameters shall be verified at the ICA. All resources shall be under program control by the Test Program Set (TPS).

3.2.1 Power Requirements.

The ARTS shall provide the necessary Direct Current (DC) and Alternating Current (AC) power supplies for power input to the LRUs listed in Table 2-1.

3.2.1.1 DC Power Stimulus. The ARTS shall provide twelve (12) simultaneous, individually programmable, variable DC power supplies. The power supplies shall have the capability to be individually programmable and operated manually. Each supply shall comply with the following requirements:

A floating type output to allow the output to be configured as a positive or negative power source.

Sense lines provided at the ICA for remote sensing.

Programmable voltage with over-voltage protection output through full range to its maximum limit.

Programmable current limit with over-current protection.

Front panel indication of output status for normal operation or fault occurrence.

Provide the amount of current draw via software to the test executive described in paragraph 3.2.6.2.

The ARTS shall provide, at a minimum, the DC power stimuli as described in Table 3-1 below. Table 3-1 provides the minimum performance parameters of the DC power stimuli that are required for power input to the LRUs listed in Table 2-1. Note that only one LRU will be tested at a time on ARTS. All specified parameters shall be verified at the ICA.

Parameter Requirement

DC No. 1 Programmable Voltage Range 0 to +50 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max.

Current Range 0 to 10 A Current Limit Accuracy: ± 70 mA Output Power: 500 W

DC No. 2 Programmable Voltage Range 0 to -50 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3%

Ripple ± 50mV p-p max.

Current Range 0 to 15 A Current Limit Accuracy: ± 70 mA Output Power: 750 W

DC No. 3 Programmable Voltage Range 0 to +28 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max.

Current Range 0 to 6 A Current Limit Accuracy ± 70 mA Output Power 175 W

DC No. 4 Programmable Voltage Range 0 to -28 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max.

Current Range 0 to 6 A Current Limit Accuracy ± 70 mA Output Power 175 W

DC No. 5 Programmable Voltage Range 0 to +24 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max.

Current Range 0 to 2 A Current Limit Accuracy ± 70 mA Output Power 50 W

DC No. 6 Programmable Voltage Range 0 to -24 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max.

Current Range 0 to 2 A Current Limit Accuracy ± 70 mA Output Power 50 W

DC No. 7 Programmable Voltage Range 0 to +20.5 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max Current Range 0 to 17 A Current Limit Accuracy ± 70 mA Output Power 350 W

DC No. 8 Programmable Voltage Range 0 to -20.5 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max.

Current Range 0 to 17 A Current Limit Accuracy ± 70 mA Output Power 350 W

DC No. 9 Programmable Voltage Range 0 to +13 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max.

Current Range 0 to 3 A Current Limit Accuracy ± 35 mA Output Power 40 W

DC No. 10 Programmable Voltage Range 0 to -13 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 50mV p-p max.

Current Range 0 to 3 A Current Limit Accuracy ± 35 mA Output Power 40 W

DC No. 11 Programmable Voltage Range 0 to +9 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 30mV p-p max Current Range 0 to 60 A Current Limit Accuracy ± 250 mA Output Power 540 W

DC No. 12 Programmable Voltage Range 0 to -9 Vdc Programmable Resolution 250 mV Voltage Accuracy ± 3% Ripple ± 30mV p-p max Current Range 0 to 60 A Current Limit Accuracy ± 250 mA Output Power 540 W

Table 3-1 DC Power Stimulus

3.2.1.2 AC Power Stimulus. The ARTS shall provide two (2) simultaneous, individually programmable AC power supplies. The power supplies shall have the capability to be individually programmable and operated manually. Each supply shall comply with the following requirements:

Sense lines provided at the ICA which can be connected to the load for remote sensing or they can be left unconnected for local sensing. If the sense lines are left unconnected, the power supply shall automatically use local sensing.

Programmable voltage with over-voltage protection output through full range to its maximum limit.

Programmable current limit with over-current protection.

Front panel indication of output status for normal operation or fault occurrence.

Provide the amount of current draw via software to the test executive described in paragraph 3.2.6.2.

The ARTS shall provide, at a minimum, the AC power stimuli as described in Table 3-2 below. Table 3-2 provides the minimum performance parameters of the AC power stimuli that are required for power input to the LRUs listed in Table 2-1. Note that only one LRU will be tested at a time on ARTS. All specified parameters shall be verified at the ICA.

AC1 Voltage (programmable) 0 to 230 Vrms Programmable Resolution 1 Vrms Voltage Accuracy ± 2.5 % of output voltage Frequency (programmable) 60 Hz to 400 Hz Programmable Resolution 1 Hz Frequency Accuracy ± 5 % Number of Phases 3-phase : ØA, ØB, ØC Programmable Phase

Resolution

1.0 degree

Programmable Phase Accuracy 1% per 100 Hz Max Current 25 A per phase Output Power 17250 VA

AC2 Voltage (programmable) 0 to 100 Vrms Programmable Resolution 1 Vrms Voltage Accuracy ± 5 % of output voltage Frequency (programmable) 60 Hz to 400 Hz Frequency Accuracy ± 5 % Number of Phases 3-phase : ØA, ØB, ØC Programmable Phase

Resolution

1.0 degree

Max Current 3.5 A per phase Output Power 1050 VA

Table 3-2 AC Power Stimulus

3.2.2 Analog Instrumentation Requirements

3.2.2.1 Analog Stimulus. The ARTS shall provide 2 Arbitrary Function Generators (AFG) with external Amplitude Modulation Inputs and 2 Pulse Generators which can be program controlled to connect to any one or all of coax outputs of ICA.

The AFG and pulse generator output switching matrices shall provide programmable source impedances of 50 Ω, 75 Ω and 93 Ω. In addition, the ARTS shall provide a 20MHz and a 40 MHz Sinewave Stimulus output with specifications listed in Table 3-3.

All specified parameters shall be verified at the ICA.

Parameter Requirements AFG Signal Characteristics (Sine, Square, Triangular Wave, or any combination) DC Offset Range ± 5.0 Vdc DC Offset Accuracy ± .5 Vdc Max Rise/Fall Time 100ns (10 to 90%) Linearity (Triangular wave) ±3% to 240KHz AFG Low Voltage Output Specifications Frequency Range 1 Hz to 2 MHz Frequency Accuracy ± 0.1%

Voltage Range 0 to ± 10 Vp-p into 50, 75, 93 Ohms

Voltage Accuracy (Full Scale) <1 MHz 1 MHz to 2 MHz

± 2% ± 4%

Max Current 100 mA AFG High Voltage Output Specifications Frequency Range 1Hz to 6 KHz into < 50 Ohms Frequency Accuracy ± 0.1% Voltage Range 0 ± 122 Vp-p Voltage Accuracy (Full S l ) ± 3% Max Current 500 mA Pulse Generator Specifications Repetition Rate 0.5 Hz to 16 MHz Pulse Width 20 ns to 100 ms

Pulse Width resolution

20 ns, 20 ns ≤ PW < 10 µs 500 ns, 10 µs ≤ PW < 100 µs 1 s, 100 µs ≤ PW < 1 ms 1 ms, 1 ms ≤ PW < 100 ms

Pulse Amplitude Voltage Range

± 20 Vp (max ± 20 V pulse)

Voltage Accuracy ± 3% of setting, ± 50mVp Delay 20 ns to 1.6 sec Delay resolution

20 ns, 20 ns ≤ Delay < 10 µs 1 µs, 10 µs ≤ Delay < 1 ms

100 µs, 1 ms ≤ Delay < 100 ms 1 ms, 100 ms ≤ Delay < 1.6 s

Pulse DC Offset

± 20 Vdc (pulse signal within ± 20 V range)

Rise/Fall Time 5 ns to 500 ns

Rise and Fall Time resolution 5 ns, 5 ns ≤ R/F < 50 ns 10 ns, 50 ns ≤ R/F < 200 ns 20 ns, 200 ns ≤ R/F ≤ 500 ns

20MHz Sinewave Stimulus Frequency Accuracy 20 MHz ± 60Hz Output Level Capacity 3.75 Vp-p into 95 Ohm 40MHz Sinewave Stimulus Frequency Accuracy 40 MHz ± 120Hz Output Level Capacity 3.75 Vp-p into 50 Ohm Programmable Square Wave Voltage Range ± 20 V Voltage Resolution 100 mV Frequency Programmable 1 Hz to 3 MHz

Frequency Resolution

1 Hz, 1 Hz to 1 KHz 10 Hz, 1 KHz to 100 KHz 100 Hz, 100 KHz to 3 MHz

Frequency Accuracy

For programmed frequency of 1 Hz to less than or equal to 200 Hz, accuracy is ± 10 Hz For programmed frequency greater than 200 Hz, accuracy is ± 1% of programmed value.

Drive Capacity 95 ohms Undershoot Overshoot ± 5 percent maximum

Table 3-3 Analog Stimulus

3.2.2.2 Analog Signal Measurement. The ARTS shall provide 2 independent measurement channels at the ICA with 2/4-wire capability to measure signals with parameters listed in Table 3-4. The measurement channels shall also be available at the ICA through two 1X32 dedicated switching matrices and 2 probe panel inputs. The measurement switching matrices shall provide programmable termination impedances of 50 Ω, 75 Ω, 93 Ω, and default 1MΩ.

DC Voltage Voltage Range ± 100 mV to ± 512 V

Accuracy ± 0.05% of range or ± 100 µV whichever is greater

AC Voltage Voltage Range

10 mVrms to 200 Vrms, 10 Hz to 50 Hz 10 mVrms to 500 Vrms, 50 Hz to 5 KHz 10 mVrms to 200 Vrms, 5 KHz to 300 KHz 10 mVrms to 100 Vrms, 300 KHz to 1 MHz

Frequency Range 2 Hz to 50 MHz

Voltage Accuracy

2Hz to 5kHz: ±0.25% of range or ±100 µV, whichever is greater

5kHz to 50kHz: ±0.5% of range or ±100 µV, whichever is greater

50kHz to 300 KHz: ±1.0% of range or ±100 µV, whichever is greater

300 KHz to 50 MHz: ±2.0% of range or ± 270 µV, whichever is greater (± 6% on 100 Vrms)

External Trigger 1 each channel DC Current Derived from LRU testing requirements AC Current Derived from LRU testing requirements Resistance Range 0.1 ohms to 10 Mohms Accuracy ± 0.05 % of range (2/4 wire capability)

Table 3-4 Analog Signal Measurement

3.2.2.3 Waveform Analysis. The ARTS shall provide the capability to perform frequency measurement, time measurement and amplitude analysis on two independent channels at the ICA. All measurements shall be under computer control and shall have the capability of being initiated by either internal or external gates and/or triggers. Waveform measurements shall be digitized, available to the ARTS computer for analysis, and displayable on the CRT.

Analysis/measurement capability shall be provided for signals within characteristics ranges as listed in Table 3-5. The waveform analysis channels shall also be available at the ICA through two 1X8 dedicated switching matrices and 2 probe panel inputs. The measurement switching matrices shall provide additional programmable termination impedances of 50 Ω, 75 Ω, 93 Ω, and 1M Ω.

Frequency Range 1 Hz to 200 MHz Sample Rate 2 Gs/s Waveform Sinusoidal or Pulsed Input Voltage 30 mVp-p to 1000 Vp-p Interface Impedance, selectable 50 ohm and 1 Mohm Trigger Delay 0 to 3600 Sec in 10µs step

External Trigger < 1ms Analysis Capabilities

Peak Voltage 512 Volts Max Peak to Peak Voltage Range 1000 Volts Max

2 Hz to 5 KHz, + 0.25% F.S.

5 KHz to 50 KHz, + 0.5% F.S.

50 KHz to 1 MHz, + 1.0% F.S.

1 MHz to 5 MHz, + 2.0% F.S.

5 MHz to 10 MHz, + 4.0% F.S.

Over/Undershoot/Ringing Range 0 to 25% of peak amplitude Accuracy + 5% of measured peak amplitude Ringing Period Range 100 ns to 500 ns

DC Offset Range 0 to 100 Volts Accuracy + 0.25% of range

Table 3-5 Waveform Analysis

3.2.2.4 Frequency/Time/Pulse Measurement Requirements. For all frequency/time measurements the ARTS capability shall include a minimum of 2 independent input channels for channel-to-channel comparative measurement and pulse measurement as listed in Table 3-6.

The frequency/time/pulse measurement channels shall also be available at the ICA through 2 1x8 dedicated switching matrices and 2 probe panel inputs. The frequency/time/pulse measurement switching matrices shall provide programmable termination impedances of 50 Ω, 75 Ω, 93 Ω, and default 1M Ω.

Parameter Requirement Sinusoidal Waveform Frequency Requirements

Frequency Range 1 Hz to 50 MHz Time Base Accuracy ± 0.12 p/m

Frequency Resolution ≤ 0.1 Hz for Fc ≤ 100 Hz ≤ 10 Hz for 100 Hz ≤ Fc 10 MHz

Time Interval Measurement Requirement Time Range 0 to 32767 at 1ms and 1s resolution Voltage Range ± 512 V

Vmax of test equipment impedance at: 50 Ω 14.1 VTRMS

75 Ω 17.3 VTRMS

93 Ω 19.2 VTRMS

Pulse Measurement Requirement

Input Signal Amplitude 30 mVpp to 32 Vpp Duty Cycle Range < 0.5 Time Interval, Time Range 0 to 32767 s at 1 ms and 1 s resolution Voltage Range ± 512 V

Vmax of test equipment for impedance:

50 ohm: 14.1 VTRMS 75 ohm: 17.3 VTRMS 93 ohm: 19.2 VTRMS

Pulse Width 20 ns to 100 ms

Pulse Width Resolution < 20 ns for PW < 10 µs < 500 ns for 10 µs <PW < 1 ms < 1µs for 1 ms <PW < 100 ms

Pulse Width Accuracy

+ 10 ns + TE* for PW < 500 ns + 20 ns + TE for 500 ns < PW < 10 µs + 500 ns + TE for 10 ns < PW < 100 ms

Channel to Channel Delay 5 ns to 64 Seconds

Delay Resolution

5 ns for Delay ≤ 1 µs 20 ns for 1 µs < Delay ≤ 10 µs 1 µs for 10 µs < Delay ≤ 64 s

Delay Accuracy for 20 ns < Delay < 1 µs, ± 7 ns ± TE for 1 µs < Delay < 10 µs, ± 20 ns ± TE for 10 µs < Delay < 4 S, ± 1 µs ± TE for 4 s < Delay < 64 S, ± 13 µs ± TE

Rise/Fall Time 5 ns to 500 ns, 900 mV Min

Rise/Fall Time Resolution 5 ns for Rise/Fall Time ≤ 100 ns 10 ns for 100 ns ≤ Rise/Fall Time 500ns

* TE = Trigger Error

Table 3-6 Frequency/Time Measurement Requirements

3.2.2.5 Discrete Signals I/Os. The ARTS shall provide simultaneous, individually programmable analog signal source/measurement channels. Each I/O channel shall be capable of generating/measuring either a differential or single-ended discrete signal. LV and HV parallel discrete I/O channels shall be programmable as source or measurement channels in groups of 4 or less. The LV and HV parallel discrete channels shall be individually programmable in output voltage amplitude on each channel within the voltage ranges specified in Table 3-7. Two level sets shall be provided per 16-channel group. The 28 & 73 V discrete channels shall be partitioned in groups of 22 or less for amplitude programming.

Logic 1 and 0 shall be individually, independently programmed. The output shall have the ability to be activated or deactivated from 8 “start” input signals at the ICA. A minimum of 2 simultaneous start signals shall be available for use. Each signal source shall comply with the requirements listed below in Table 3-7. All specified parameters shall be verified at the ICA. Each output channel of the LV and HV discretes shall be capable of being connected together with other LV/HV outputs for parallel operation in order to achieve currents up to 150mA for LV outputs and 250mA for HV outputs.

Parameter Requirement LV Parallel Discretes (Quantity of 264) +5 Volt Discretes Differential Voltage Range 0 to +5 V Voltage Accuracy ± 0.1 Vdc Programmable Resolution 6.7 mV Current 85mA Max Rise and Fall Time 50 ns Max Repetition Rate DC to 200 Hz ±5 Volt Discretes Voltage Range -5 to +5 V Voltage Accuracy +0.1 Vdc Programmable Resolution 6.7 mV Current 85 mA Max Rise and Fall Time 500 ns Max Repetition Rate DC to 200 Hz ±12 Volt Discretes Voltage Range -12 To +12 V, 12 V max swing Voltage Accuracy 1% setting to + 50 mV Programmable Resolution 6.7 mV Current 65 mA Max Rise And Fall Time 500 ns Max Repetition Rate DC To 200 Hz 28 & 73 VDC Discretes (Quantity of 114 single ended or 57 differential) +28 Volt Discretes Voltage Level 0 or + 28 (± 1.0) Vdc Current 140 mA Max Rise And Fall Time < 1 ms 73 Volt Discretes Voltage Level 2.5 or + 73 (± 1.0) Vdc Current 1.0 mA Rise And Fall Time < 2 ms HV Parallel Discretes (Quantity of 48) ±30 Volt Discretes Voltage Range - 31 To + 31 V, 31 V max swing Voltage Accuracy 1% setting to + 50 mV Programmable Resolution 100 mV (0-5V), 500 mV

(>5V) Current 50 mA Max Rise And Fall Time 500 ns Max Repetition Rate DC To 200 Hz

Table 3-7 Discretes Signals

3.2.2.5.1 Discrete Signal Measurement. The ARTS shall provide, under program control, a minimum of 264 simultaneous LV parallel digital inputs for a threshold detection range of - 12V to +12V. The ARTS shall provide, under program control, a minimum of 48 simultaneous HV parallel digital inputs for a threshold detection range of

- 31 to +31V. During single-ended mode, either the Hi and Lo pins of each channel shall be capable of threshold detection.

3.2.2.6 Vector Voltage and Phase Measurement. The ARTS shall provide under computer control the Vector Voltage and Phase measurements as specified in Table 3- 8 below:

Parameter Requirement Voltage Measurements Total (Vector) Fundamental in phase quadrature Frequencies 400 ± 20 Hz and 800 ± 40 Hz Range 0.0625 Volts to 512 Volts in decade steps Accuracy ± 0.5% or range Resolution 0.1% Phase Angle Measurements Range ± 179.9 degrees Accuracy ± 1 degree Resolution 0.5 degree

Table 3-8 Vector Voltage and Phase Measurement

3.2.2.7 DC Stimulus. The ARTS shall provide 15 DC stimuli outputs, which may be driven by 6 independently programmable precision voltage outputs. Each signal shall meet the requirements listed in Table 3-9 using 4-wire sense lines or other methods to ensure accuracy and resolution. All specified parameters shall be verified at the ICA.

Parameter Requirement Voltage - 31 to + 31 Vdc

± 2 V: ± 0.02% of setting ± 600 µV ± 20 V: ± 0.02% of setting ± 2.4 mV ± 31 V: ± 0.02% of setting ± 7.2 mV

Resolution

± 2 V: 0.05 mVdc ± 20 V: 0.5 mVdc ± 31 V: 1.5 mVdc

Current 800 mA

Table 3-9 DC Stimulus

3.2.2.8 AC Stimulus. The ARTS shall provide programmable AC signal sources. Each signal source shall comply with the requirements listed in Table 3-10. All specified parameters shall be verified at the ICA.

Programmable voltage and current Programmable frequency

Parameter Requirement 2000 Hz Sine Wave Modulator Carrier (UUT Provided) (a) Input Characteristics: 0 to 5V pk max.

single ended

(b) Input Impedance: 50 ohms to 2 Kohm selectable

Characteristics: The modulation shall simulate the output signal containing relative position and rate or change information from an inductive linear transducer Output Voltage Envelope: 0 to 5 Vrms ± 2% of full scale Modulating Signal Frequency: 0.1 to 32 Hz ± 1% Maximum Current: 50 mA

400 Hz Sine Wave Modulator Carrier (externally provided or internally provided by an AC source)

Characteristics: The modulation shall simulate the output signal containing relative position and rate or change information from an inductive linear transducer Output Voltage Envelope: 0 to 11 Vrms ± 2% of full scale Modulating Signal Frequency: 0.5 to 32 Hz ± 1% Maximum Current: 50 mA

Table 3-10 AC Stimulus

3.2.3 Digital Instrumentation Requirements

3.2.3.1 Biphase Bi-directional (BPBD) Manchester II Buses. BPBD Manchester Buses shall be provided by programmable multipurpose buses. The buses shall be capable of concurrent and coordinated activities. The BPBD controllers shall provide the envelope of functional and dynamic (timing, synchronization, and data transfer rates) capabilities as described in this paragraph and Table 3-11. The ARTS shall contain two dual redundant pairs of BPBD buses (4 ports). Each channel (dual redundant pair) shall be independent but switchable to the other. Each channel shall be programmable to transmit and receive data in accordance with MIL-STD-1553B (Port Qty: 4 I/O channels, 2 redundant pairs of BPBD busses).

Each channel shall be capable of performing send and receive communications within the nominal limits specified herein. All programmability specified, with the exception of amplitude variations, shall be programmable for all channels. Amplitude programming shall be provided for one channel of each pair and the channel is selectable under program control.

All specified parameters shall be verified at the ICA. Nominal and Programmable Features:

Parameters Nominal Programmable Range

Bit Rate 1 MHz (±0.1) percent

0.90 MHz or 1.1 MHz in equally

spaced increments of ≤2.0 kHz.

Output Voltage

0.4 to 20V pp (±10%) line-to-line differential terminated with 75 (±10%) ohms

Output Voltage Resolution

100 mV increments

Word size 16 to 24 bits in 1/2-bit increments Word message (after command word)

1 to 32 words

Sync word width

3.0 microseconds (±3%)

1 to 3 bit times in 1/2-bit increments

Bit width 1 microsecond (±0.1%)

Sync Time Transition 0.25 to 4 us in 1/2-bit time increments Parity Odd Even or Odd Parity Rise time, fall time (output)

150 ns (±50) ns at 1 MHz

Impedance 75 ohms (±10%) Channel data memory (stimuli and response)

4K bits deep each

Input voltage

0.4 to 27V pp (±10%) (shall present 75 ohms (±10%) passive load to the UUT transmitter)

Input Voltage Resolution

100 mV increments (shall not respond to signal less than programmed value.)

Intermessage gap 4 s to 32 s (1 s increments) Intermessage 0.000 (±0.075V) pp Delay between programmable redundant channels

0 to 20 s (1 s increments)

Table 3-11 Biphase Bi-directional (BPBD) Manchester II Buses

ADDITIONAL REQUIREMENTS

1. UUT Response Time. A UUT response time window shall be programmable starting 4 microseconds after last transmission in increments of 1 s to a maximum width of 4 ms. This window represents the maximum time that a receiver channel shall wait before determining that the UUT has not responded.

2. Channel Response Time. The channel response time window shall be programmable from 4 s to 4 ms in 1 s increments. This represents the test station response time (start of status word) with respect to the reception of a valid command word from a UUT.

3. Short Circuits. The output circuits shall be capable of sustaining a short circuit to ground without any damage.

4. Error Storage. Received Manchester data shall be checked for Manchester errors within it. Storage of the word locations and bit error numbers shall be provided. Memory storage capacity shall be 4k bits minimum.

5. Invalid Test Patterns. Transmitted Manchester data shall be capable of generating invalid Manchester codes as follows:

(a) Invalid data bit - no transition. Program invalid Manchester code (no transition) for any bit of any word in a message.

(b) Invalid Manchester code in data field

(c) Incorrect Parity

6. Invalid Sync. The transmitted data shall be capable of providing invalid sync transitions.

7. Word Validation. Each channel shall have the capability of issuing to the host computer the status of each received Manchester message. The status shall contain information describing the conformance of the following parameters:

(a) Sync field agrees with programmed values.

(b) Bit pattern error - received data was valid Manchester code and bit word pattern was formatted as programmed.

(c) Parity correct as programmed.

(d) Failure of UUT to respond to input commands and/or messages.

8. Parity Bit (Transmit). A parity bit in the last position of a received/transmitted word shall be programmable as even or odd.

3.2.3.1.1 Channel Output/Input Signals. The following signals shall be available at the station interface.

a. Data. The DATA and DATA NOT TTL differential signals for each of the channels (two differential pairs are required).

b. Sync Clock. A test clock shall be available for providing a time reference for external equipment. The clock shall be free-running and synchronized with the data. The level shall be TTL compatible and capable of sinking 40 mA. There shall be one clock for each channel (two, total).

c. Sync Gate. The sync signal shall provide a gating signal for external equipment to indicate channel activity. The sync gate is generated at the start of any sync pulse until the end of bus activity. The level shall be TTL compatible and capable of sinking 40 mA. There shall be one gate for each channel (total of two).

3.2.3.2 Bipolar Return-to-Zero (RZ) Serial Data. The ARTS shall provide 16 channels which can be programmed in any of the Type A, B, or C listed below. The ARTS shall be capable, under program control, of selecting each mode of operation; i.e., to transmit or receive as specified herein.

3.2.3.2.1 Self Clocking

a) Type A. A Type A Bipolar RZ self-clocking line shall consist of only one pair of Data lines, either the Data Input Pair or the Data Output Pair. Total port quantity shall be 16 pairs of Type A.

b) Type B. A Type B Bipolar RZ self-clocking channel shall be comprised of only two of three pairs of lines. The pairs shall consist of the Data Input/Output Enable Address with either the Data Input pair or the Data Output Pair. Total port quantity shall be 16 sets of 2 pairs of Type B.

c. Type C. A Type C Bipolar RZ self-clocking serial data channel shall be capable of using three pairs of lines to simulate the role of LRU "A" or LRU "B", as per Figure 3-1. The ARTS shall also be capable of configuring as a Type C channel such that the source of the address is the opposite (with respect to Data Input/Output flow). Total port quantity shall be 16 sets of 3 pairs of Type C.

In each case, (Type A, B, C) the ARTS shall also be capable of providing the timing and digital format as indicated in Figures 3-2 thru 3-4.

The above RZ data shall conform to the requirements of L409C2011 Type III and below:

1. Programmability - Each pair of lines within a channel shall be available simultaneously and each parameter shall be independently programmable.

Message lengths and word size shall be individually programmable in accordance with Figures 3-1 through 3-5.

2. Invalid Test Patterns - The ARTS shall be capable of generating invalid codes as follows:

(a) Invalid data bit, no transition, for any or all bits of a word(s).

(b) Incorrect Parity

d. Type D. Other Buses. The additional buses are required as specified below:

1. A Type D-1 Bipolar RZ self clocking line shall consist of only one pair of data lines (total of 8 pairs). All parameters specified in Table 3-12 shall be verified at the ICA.

Serial Data 16 Bit Word

Data Characteristics Signal HI Signal LO

VOLTAGE LEVEL

Logic 0 -5 (±1) V +5 (±1) V Logic 1 +5 (±1) V -5 (±1) V

Clock Rate 400 (±40) Hz or 1.0 (±30KHz) MHz

Output Drive 600Ω resistive load in parallel with 0.03μF

Table 3-12 Type D-1 Bipolar RZ Serial

2. A Type D-2 Bipolar RZ self clocking line(s) shall consist of one pair of data lines (total of 8 pairs). All parameters specified in Table 3-13 shall be verified at the ICA.

Serial Data Four 32 bit words with 32 bit word gap (224 bit message length)

Data Characteristics Signal HI Signal LO

VOLTAGE LEVEL

Logic 0 -5 (±1) V +5 (±1) V Logic 1 +5 (±1) V -5 (±1) V

Clock Rate 11 (±3.5) KHz

Output Drive 600Ω resistive load in parallel with 0.03μF

Table 3-13 Type D-2 Bipolar RZ Serial

e. Attenuated Signals. The ARTS shall be capable of providing and receiving the

Types A, B, C, D-1 and D-2 RZ signals on four (4) independent channels at an attenuated voltage amplitude of 0 to ±2.5Vdc.

Figure 3-1 Mode 1 Bipolar RZ Interface

Figure 3-2 Bi-Polar RZ Timing

Figure 3-3 Bi-Polar RZ Timing

Figure 3-4 Bi-Polar RZ Timing

Figure 3-5 Bi-Polar RZ Timing

3.2.3.2.2 Bipolar Return-to-Zero (RZ) - Separate Clock. The test station shall be capable of receiving and transmitting bipolar RZ data on four (4) independent channels.

Each channel shall consist of a clock line, data line, and strobe line and shall each be capable of interfacing with the UUT. The clock lines, data lines, and strobe lines shall be double-ended. The strobe lines and clock lines shall be TTL compatible and capable of source sinking 40 mA. Each channel shall be capable of transmitting or receiving as directed under program control.

3.2.3.3 Pulse Width Modulation

The ARTS shall have the capability of transmitting and receiving serial digital pulse width modulated data. Four pairs of interface pins shall be provided at the ICA.

a. The pulse width modulated data shall have the characteristics as shown in Table 3-14. All specified parameters shall be verified at the ICA.

Frequency Modulation 6400 or 7200 Bits per second Pulse Width (See Figure 3-6) Sync Pulse = 32μS wide Binary 1 = 64μS wide Binary 0 = 96μS wide

Sync 64th bit is Sync bit Word Size 64 Bits, no gaps between words continuous transmission Driver TTL Compatible, balanced SN55114 or equivalent Voltage Levels Line A Line B Logic 0 < 0.4 Volts > 2.0 Volts Logic 1 > 2.0 Volts < 0.4 Volts

Table 3-14 Pulse Width Modulation

b. The pulse width modulation format shall be as follows:

Binary 1 = 64 s wide Binary 0 = 94 s wide Synch Pulse = 32 s wide

1. A positive edge defines start of bit.

2. Pulse width defines whether bit is binary 1, binary 0 or a synch bit.

3. Sixty-four bits define a word.

4. Sync pulse defines start of word.

5. There are no gaps between words (continuous transmission).

6. The bit pulse rate of a word (frequency of positive edges) shall be selectable

(6400 bps or 7200 bps). The bit rate within a word shall be constant.

c. The ARTS shall provide an additional pair of differential line that shall be in binary form and in sync with the Pulse Width Modulated data. The characteristics and specifications shall be in accordance with the requirements depicted for the PWM data.

Figure 3-6 Pulse Width Modulation

LINE A

LINE B

> 2.0V

> 2.0V

< 0.4V

< 0.4V

3.2.3.4 10V Logic Non-Return to Zero (NRZ) Serial Bus. The ARTS shall provide 4 independently programmable unidirectional serial buses that shall contain the characteristics in Table 3-15. All specified parameters shall be verified at the ICA.

Characteristic Requirement Clock

Clock Format Square wave, Interrupted, Differential Signals Frequency

1000Hz ± 15%

Duty Cycle 24 cycles ON, 8 cycles OFF

Sync Data transmitted during clock ON only. Bit transitions occur at positive clock transitions.

Digital Data Type Non-Return to Zero (NRZ)

Voltage Level Signal HI Signal LO

Logic 0 0 ± 2V +10 ± 2V Logic 1 +10 ± 2V 0 ± 2V

Data and Clock Characteristics Transmitter Impedance < 150 Ω Receiver Impedance > 40 KΩ

Table 3-15 10V Logic NRZ Serial Bus

3.2.3.5 5V Logic, NRZ Serial Bus. The ARTS shall provide independently programmable unidirectional serial bus with the characteristics listed in Table 3-16.

Characteristic Requirement Signal Format NRZ, ASCII Voltage Levels Ref RS 422/423 Drive Capability Ref RS 422/423

Data Format 132 bits per word and 3 words per transmission with random spacing between words

Data Rate 9600 Baud Parity Odd

Table 3-16 5V Logic NRZ Serial Bus

3.2.3.6 Additional Digital Interface Buses. The ARTS shall be capable of providing communication with the digital buses listed in Table 3-17. All specified parameters shall be verified at the ICA.

Interface Buses Parameter Requirement

RS 232

Operating Mode Transmit / Receive

Number of Channels 2 (independently programmable)

Buffer Size

Transmitter - 64K words Receiver - 64K words

Baud Rate

Programmable from 1200 to 19200 baud 7 or 8 bit data, Programmable start, stop and parity bits

Parity Odd or Even parity

RS 422

Operating Mode Transmit / Receive

Number of Channels 2 (independently programmable)

Buffer Size Transmitter - 64K words Receiver - 64K words

Baud rate

Programmable from 1200 to 19200 baud 7 or 8 bit, data, start, stop and parity bits

Parity Odd or Even Parity

Table 3-17 Digital Interface Buses

3.2.3.7 Digital Parallel Stimulus/Measurement Capability. The Parallel Stimulus/Measurement Capability shall consist of a control subsystem with programmable micro-sequencer operating characteristics. Control and sequencing of test data input and output shall be provided through line-by-line execution of control codes (protocol instructions). Control codes shall be stored locally within the subsystem and initialized by download from the test station host processor.

The Parallel Stimulus/Measurement Capability shall be used for simulation of a variety of parallel digital bidirectional (transmit and receive) buses. Messages to be transferred over these buses shall be stored in a Pattern Memory contained within the Parallel Stimulus/Measurement Capability. Patterns shall be initialized from the test station host processor by download.

There shall be a minimum of 8 independent parallel bus controllers with a total of 256 differential or single ended I/O channels at the ARTS ICA. Each parallel bus controller shall control at least 32 I/O channels each.

Logic 1 and 0 shall be individually, independently programmed. I/O channels shall be programmable in input voltage, output voltage, output current and single/differential mode in groups of 8 or less. Channels shall be programmable as input or output in sub-groups of 4 or less. The LV and HV parallel channels shall be individually programmable in output voltage amplitude on each channel within the voltage ranges specified in Table 3-18. Two level sets shall be provided per 16-channel group. Each parallel controller’s internal clock shall be externally available at the ICA. A strobe signal shall be available at the ICA indicating when input data is transmitted to the UUT. At a minimum, each parallel bus controller shall have an externally provided start, gate and sync input at the ICA. Each signal source shall comply with the requirements listed below and in Table 3-18. All specified parameters shall be verified at the ICA.

Parameter Requirement LV Parallel I/O (Quantity of 232) Voltage Amplitude Range -12 To +12 V, 12 V max swing Voltage Accuracy ± 1% setting + 50 mV Programmable Resolution 6.7mV output, 0.1 input Programmable Max Current 0 to 85mA HV Parallel I/O (Quantity of 24) Voltage Range -31 To +31 V, 31 V max swing Voltage Accuracy ± 1% setting + 50 mV Programmable Resolution 17.1mV output, 260mV input Programmable Max. Current 0 to 65mA Data Rate DC To 10MHz

Table 3-18 Parallel I/O Signals

3.2.3.7.1 Bi-directional Buses. Bi-directional buses in the ARTS shall be capable of performing as a master or a slave depending on the UUT. They will be independently programmable.

3.2.3.7.2 Unidirectional Buses. Unidirectional buses shall be independently programmable.

3.2.3.7.3 Differential TTL I/O and TTL Buffers. The ARTS shall provide at least 25 TTL compatible I/O tri-state buffers and 25 differential TTL I/O driver circuits. The refresh rate shall be 5ns or faster.

3.2.3.7.4 CMOS Buffers. The ARTS shall provide at least 25 CMOS compatible I/O buffers. The refresh rate shall be 20ns or faster.

3.2.3.7.5 ECL Input/Output. The ARTS shall provide 4 ECL Programmable Clocks.

The clocks shall be derived from, and synchronous with any of the reference stimuli available for digital timing subsystem. The derived clocks shall have the following characteristics as listed in Table 3-19. Also, the ARTS shall provide 4 identical word generators. Each can output a 1 bit pattern up to 4096 words. Each output data pattern shall be repeatable for up to 255 times, selectable between RZ and NRZ modes.

External data can also be input into the word generator. All specified parameters shall be verified at the ICA.

Parameter Requirement ECL Clock Input/Output Clock Frequency Range 1 MHz to 25 MHz Resolution 10 ns or 1% of Clock Period Differential Output Level

Logic ‘1’ Logic ‘0’

-1.750 V ± 0.1 V -0.885 V ± 0.075 V

Line Driver Impedance 50 Ohm Differential 50 MHz ECL Input/Output Frequency Accuracy 50 MHz ± 150 Hz Line Driver Impedance 50 Ohm ECL Data Input/Output Word Generators Frequency Accuracy 50 MHz ± 150 Hz Line Driver Impedance 50 Ohm

Table 3-19 ECL Input/Output

3.2.4 RF Instrumentation Requirements. ARTS shall provide RF stimuli and measurement switching and signal conditioning capabilities, and capability for measuring narrow- and wide-bandwidth detected/demodulated RF waveforms. It shall provide RF stimulus to the LRU and measurement of RF signals from the LRU.

RF stimulus includes high- and low-power CW and modulated RF. The RF stimulus function attenuates, amplifies, or modulates the selected RF input and switches it to a selected output for routing to the LRU. Signal conditioning applied to stimuli includes attenuation, power amplification, and narrow-band to wide-band filtering. Modulation of RF stimuli includes amplitude modulation (AM), frequency modulation (FM), pulse, pulse amplitude modulation (PAM), and biphase modulations.

RF measurement includes RF measurements and demodulated signal measurements of LRU signals, to include precision frequency,…