Tab 04 ADaPT GEN III PCB Fabrication Drawing 20260701.pdf

PDF 1 MB Posted Jul 7, 2026

Attached to: ADaPT Gen III PCB Fabrication/Assembly
Solicitation number: 80NSSC26933620Q
Issued by: National Aeronautics and Space Administration Shared Services Center

About this file

Written by GovTribe AI · Jul 7, 2026

This is a NASA Glenn Research Center PCB (Printed Circuit Board) Fabrication Drawing for the ADaPT GEN III PCB, a complex multi-layer circuit board design. The drawing specifies detailed manufacturing requirements for a preliminary-stage printed wiring board utilizing EM-892K glass cloth epoxy laminate material with multiple copper signal layers and dielectric layers totaling 63.16 mils in thickness.

The fabrication requirements mandate compliance with IPC-2221, IPC-2222, and IPC-2228 (Type 4) design standards, with fabrication, inspection, and acceptance criteria per IPC-6012 Class 2. The board features nine copper layers (GND 1, RF1, GND 2, Control, Power, GND 3, SL (RF 2), and FEED (GND 4)) with specified conductor widths ranging from 0.005 inches minimum to greater widths with defined tolerances. Impedance control is required across 16 transmission line configurations with target impedances of 50 and 100 ohms. The board requires gold plating via ENIG (Electroless Nickel/Immersion Gold) finish on exposed copper areas, single-coat LPI permanent blue solder mask on both sides, and white epoxy ink silkscreen with manufacturer identification, date code, and sequential serial numbering. Electrical testing must be performed on 100% of deliverable products per IPC-6018 Class 2 Type 4, with maximum rated voltage of 28VDC and dielectric withstanding voltage testing at double the maximum rated voltage. The design incorporates controlled-depth routing, edge plating connected to GND net, chamfered edges at 45 degrees, and test coupons integrated into manufacturing panels with traceability requirements.

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Other files

File	Type	Posted
Tab 10 RFQ 80NSSC26933620Q Full and Open.pdf	PDF	Jul 27, 2026
Tab 10 RFQ 80NSSC26933620Q Updated.pdf	PDF	Jul 7, 2026
Tab 04 SOW Redacted.pdf	PDF	Jul 7, 2026
Tab 04 ADaPT GEN III PCB Assembly Drawing 20260701.pdf	PDF	Jul 7, 2026
Tab 10 RFQ 80NSSC26933620Q.pdf	PDF	May 28, 2026
Tab 04 SOW Redacted.pdf	PDF	May 28, 2026

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1 1

2 2

3 3

4 4

GND 1 (Scale 5:2)

SHEET: OF

SIZE:

NASA Glenn Research Center 21000 Brookpark Rd Cleveland, OH 44135

.It

REV: DWG NO:

SCALE:

TITLE:

=PCB_FABRICATION_DRAWING_TITLE

BOM DOC:

FAB DOC:

PCBA DOC:

SCH DOC:

Reference Documents

1 4

APPROVALS DATE

ENGINEER:

DESIGNER:

CHECKER:

FILE NAME: ADaPT GEN III PCB, Fabrication

DESIGN ITEM: DESIGN ITEM REVISION:

.Item .ItemRevision

PART NO: =PCB_PART_NUMBER

NO CHANGES BEYOND CUSTOMARY AND STANDARD BUILD PRACTICES SHALL BE MADE WITHOUT PRIOR APPROVAL FROM NASA GRC.1

PRIMARY SIDE OF BOARD SHOWN ON PAGE 1 (FABRICATION DRAWING).2

DESIGN SHALL BE IAW IPC-2221, IPC-2222, AND IPC-2228 (TYPE 4).3

FABRCATION, INSPECTION AND ACCEPTANCE CRITERIA PER IPC-6012 CLASS 2.4

MATERIAL:

A. EM-892K GLASS CLOTH EPOXY LAMINATE PER IPC-4103/134. COPPER ELECTROD EPOSITED HIGH TEMPERATURE TYPE H, THICKNESS TOLERANCE CLASS B AND SURFACE QUALITY CLASS A. SEE LAMINATE STACK UP FOR NORMAL FOIL WEIGHT, UNLESS OTHERWISE INDICATED, MINIMUM DIELECTRIC SPACING BETWEEN CONDUCTIVE LAYERS SHALL BE .0025 MINIMUM AFTER LAMINATION.

B. BONDING SHEET: EM-892K RESIN PRE-IMPREGNATED GLASS FABRIC PER IPC-41031/134.

C. COPPER FOIL: ELECTROPLATED COPPER SHEET PER IPC-4562A, HTE-TYPE E.

i. .25 OZ STARTING WEIGHT BEFORE PLATING FOR CONDUCTOR LAYERS WITH FINAL THICKNESS OF < .5 OZ

ii. .5 OZ STARTING WEIGHT BEFORE PLATING FOR CONDUCTOR LAYERS WITH FINAL THICKNESS OF 1 OZ

CONDUCTORS: DESIGNED MINIMUM ACCEPTABLE CONDUCTOR WIDTHS AND SPACING AS FOLLOWS:

A. INTERNAL/ EXTERNAL (INCH) CONDUCTOR WIDTH ≤ TO .013, +.003 -.003

B. CONDUCTOR WIDTH > TO .013 AND < .025, +.004 -.004

C. CONDUCTOR WIDTH ≥ TO .025, +.008 -.006

D. MINIMUM SPACING OF .0045

E. MINIMUM CONDUCTOR WIDTH OF .005

IMPEDANCE TO BE MAINTAINED PER TRANSMISSION LINE TABLE ON PAGE 1 OF THIS DRAWING. 7

MINIMUM ANNULAR SOLDER RING SHALL BE: .001 EXTERNAL AND .001 INTERNAL OF COPPER PAD ANNULAR RING, NOT INCLUDING HOLE PLATING MATERIAL, AROUND DRILL HOLES FOR ELECTRICAL CIRCUITS.8

SOLDER MASK:

A. APPLY A SINGLE COAT OF LPI (LIQUID PHOTO IMAGEABLE) PERMANENT BLUE SOLDER MASK ON PRIMARY (TOP) AND SECONDARY (BOTTOM) SIDE BOARD OVER BARE COPPER PER IPC-SM-840 CLASS T. FOR SOLDER MASK USE ARTWORK MASTER SUPPLIED.

FINAL FINISH:

A. EXPOSED COPPER AREAS SHALL BE PLATED WITH GOLD

i. GOLD PLATING TO BE ENIG (Electroless Nickel/Immersion Gold)

CHAMFER MARKED EDGES AT 45 DEGREES. CHAMFER TO START ON TOP LAYER WITH THE REMOVAL OF 62MILS OF MATERIAL AND TAPER TO 0MILS AT THE BOTTOM LAYER. COPPER WILL BE EXPOSED IN THE PROCESS AND CONNECTED WITH EDGE PLATING AS INDICATED IN NOTE 11.11

EDGE PLATE REQUIRED WITHIN INDICATED REGION. PLATING TO CONNECT TO NET 'GND'. PLATING TO BE 1 MIL.12

PERFORM CONTROLLED DEPTH ROUTING FROM LAYER 1 'GND 1' ALONG LINE INDICATED BY THIS NOTE. TOOL PATH DEFINED BY MECHANICAL LAYER ‘ROUTE TOOL PATH’. ROUTING TO LEAVE BETWEEN 10 – 15 MILS OF DIELECTRIC MATERIAL ABOVE LAYER 7 ‘SL (RF 2)’. 13

SILKSCREEN, LEGENDS AND OTHER NOMENCLATURE ON TOP OF THE SOLDER MASK USING WHITE EPOXY INK PER MFG INSTRUCTIONS. FOR SILKSCREEN USE ARTWORK MASTER SUPPLIED. MANUFACTURER TO CLIP SILKSCREEN THAT INTERFERES WITH SOLDER/PASTE MASKS.MANUFACTURER TO INDICATE THE FOLLOWING:

A. MANUFACTURER ID

B. DATE CODE

C. SERIAL NUMBER: STARTING AT 001 INCREMENT SERIAL NUMBER FOR EACH PCB MADE

PRINTED WIRING BOARD AND TEST COUPON TO BE DESIGNED TO THE REQUIREMENTS OF IPC-2221 CLASS 2 AND TESTED PER IPC-6018 CLASS 2 TYPE 4.

A. ELECTRICAL TEST SHALL BE PERFORMED ON 100% OF THE DELIVERABLE PRODUCT. THE ELECTRICAL PROGRAM SHALL BE EXTRACTED FROM GERBER DATA OR IPC-356 FILE.

B. FOREIGN INCLUSIONS ALLOWED: 2 PER SIDE OF BOARD.

C. LAYER TO LAYER MIS-REGISTRATION ALLOWED: MAX .003. TOTAL OF .006 OVER ALL LAYERS.

D. TOTAL MASS LOSS (TML) OUTGASSING TEST NOT REQUIRED.

E. DIELECTRIC WITHSTANDING VOLTAGE LAYER TO LAYER: PER IPC-6018. TO BE DONE ON TEST COUPON.

F. RATING: MAXIMUM RATED VOLTAGE: 28VDC. TESTING TO BE AT DOUBLE THE MAXIMUM RATED VOLTAGE.

TEST COUPONS TO BE INTEGRATED INTO PANEL PER IPC-2221 CLASS 2 ARE TO BE ADDED BY MFG.

A. TEST COUPONS TO BE TRACEABLE TO LOT AND PWB SERIAL NUMBER.

B. TEST COUPON TO BE LOCATED WITHIN .5 INCHES OF ANY BOARD ON THE PANEL.

=Scale

Impedance Id

Transmission Line

Coated Microstrip

Edge-Coupled Coated Microstrip

Offset Stripline

Edge-Coupled Offset Stripline

Offset Stripline

Edge-Coupled Offset Stripline

Offset Stripline

Edge-Coupled Offset Stripline

Offset Stripline

Edge-Coupled Offset Stripline

Offset Stripline

Edge-Coupled Offset Stripline

Offset Stripline

Edge-Coupled Offset Stripline

Surface Microstrip

Edge-Coupled Surface Microstrip

Target Impedance

Calculated Impedance

50.04

119.12

41.65

100.01

62.76

100.00

59.09

100.00

54.06

100.01

49.98

99.99

50.72

100.27

49.99

100.01

Trace layer

GND 1

RF1

GND 2

Control

Power

GND 3

SL (RF 2)

FEED (GND 4)

Wide Trace Width

10.00mil(0.25mm)

5.00mil(0.13mm)

8.00mil(0.20mm)

4.80mil(0.12mm)

5.00mil(0.13mm)

5.81mil(0.15mm)

5.70mil(0.14mm)

5.81mil(0.15mm)

5.00mil(0.13mm)

4.80mil(0.12mm)

9.26mil(0.24mm)

6.10mil(0.16mm)

9.00mil(0.23mm)

6.00mil(0.15mm)

87.72mil(2.23mm)

19.64mil(0.50mm)

Narrow Trace Width

10.00mil(0.25mm)

5.00mil(0.13mm)

8.00mil(0.20mm)

4.80mil(0.12mm)

5.00mil(0.13mm)

5.81mil(0.15mm)

5.70mil(0.14mm)

5.81mil(0.15mm)

5.00mil(0.13mm)

4.80mil(0.12mm)

9.26mil(0.24mm)

6.10mil(0.16mm)

9.00mil(0.23mm)

6.00mil(0.15mm)

87.72mil(2.23mm)

19.64mil(0.50mm)

Gap

11.00mil(0.28mm)

5.00mil(0.13mm)

Reference layers

RF1

GND 1,GND 2

RF1,Power

Control,GND 3

Power,SL (RF 2)

GND 3,FEED (GND 4)

Power

Substack

Board Layer Stack

Clearance

5.00mil(0.13mm)

Target Tolerance

20%

10%

20%

10%

20%

10%

20%

10%

20%

10%

20%

10%

20%

10%

20%

10%

Transmission Line Structure Table

8123.0mil [206.3mm]

6m il

[1 1.

9m m

] 12

1988.9mil [50.5mm]

.8 m il [8

3m m

1980.0mil [50.3mm]

6m il

[1 1.

9m m

8150.9mil [207.0mm]

3m il

[1 0.

9m m

2000.0mil [50.8mm]

Prel im ina ry

1 1

2 2

3 3

4 4

FEED (GND 4) (Scale 5:2)

SHEET: OF

SIZE:

.It

REV: DWG NO:

SCALE:

2 4

FILE NAME: ADaPT GEN III PCB, Fabrication

=PCB_FABRICATION_DRAWING_TITLE

3:2

Material Layer Thickness Dielectric Material Type Gerber

Top Overlay Legend GTO Surface Material Top Solder 1.00mil Solder Resist Solder Mask GTS Copper GND 1 2.80mil Signal GTL

Prepreg 5.00mil EM-892K Dielectric

Copper RF1 0.55mil Signal G1

Prepreg 5.00mil EM-892K Dielectric

Copper GND 2 0.55mil Signal G2

Core 5.00mil EM-892K Dielectric

Copper Control 0.55mil Signal G3

Prepreg 5.00mil EM-892K Dielectric

Copper Power 0.55mil Signal G4

Prepreg 5.00mil EM-892K Dielectric

Copper GND 3 0.55mil Signal G5

Core 20.00mil TSM-DS3b Dielectric

Core 3.90mil Composite dielectric Dielectric Copper SL (RF 2) 0.70mil Signal G6

Core 5.00mil TSM-DS3b Dielectric

Copper FEED (GND 4) 2.01mil Signal GBL Total thickness: 63.16mil

Layer Stack LegendPrel im

1 1

2 2

3 3

4 4

Drill Drawing View (Scale 3:2)

Symbol Count 8334 Total

Hole Size 7.00mil(0.18mm)

Plated Plated

Drill Layer Pair

[UVIA] GND 1 - RF1

Hole Tolerance +/-2.00mil(0.05mm)

Drill Table

Symbol Count 8078 Total

Hole Size 7.00mil(0.18mm)

Plated Plated

Drill Layer Pair

[UVIA] RF1 - GND 2

Hole Tolerance +/-2.00mil(0.05mm)

Drill Table

Symbol Count 5623 Total

Hole Size 7.00mil(0.18mm)

Plated Plated

Drill Layer Pair [UVIA] GND 2 - Control

Hole Tolerance (Mixed)

Drill TablePrel im

1 1

2 2

3 3

4 4

Drill Drawing View (Scale 3:2)

Symbol Count 1708 Total

Hole Size 12.00mil(0.30mm) 27.56mil(0.70mm) 33.00mil(0.84mm) 34.00mil(0.86mm) 45.28mil(1.15mm) 47.24mil(1.20mm) 57.09mil(1.45mm) 170.00mil(4.32mm)

Plated Plated Plated Non-Plated Non-Plated Plated Non-Plated Non-Plated Non-Plated

Drill Layer Pair

GND 1 - FEED (GND 4)

Hole Tolerance +/-3.00mil(0.08mm)

+/-1.97mil(0.05mm)

(Mixed) +/-1.97mil(0.05mm)

Drill Table

Symbol Count 5623 Total

Hole Size 7.00mil(0.18mm)

Plated Plated

Drill Layer Pair [UVIA] GND 2 - Control

Hole Tolerance (Mixed)

Drill Table

Symbol Count 5338 Total

Hole Size 7.00mil(0.18mm)

Plated Plated

Drill Layer Pair [UVIA] Control - Power

Hole Tolerance (Mixed)

Drill Table

Prel im

File details come from the government source that posted it. Updated Jul 7, 2026.