Tab 04 ADaPT GEN III PCB Assembly Drawing 20260701.pdf

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ADaPT Gen III PCB Fabrication/Assembly
Solicitation number
80NSSC26933620Q
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This is a Printed Circuit Board (PCB) assembly drawing for the ADaPT GEN III Test PCB, prepared by NASA Glenn Research Center (GRC) located at 21000 Brookpark Road, Cleveland, OH 44135. The document provides detailed assembly, soldering, and inspection specifications for manufacturing a multi-layer PCB assembly with surface mount technology (SMT) and through-hole components. Key assembly requirements include: installation of SMT parts before through-hole parts; lead-based, no-clean solder formula compliance; adherence to J-STD-001 Class III and IPC-A-610 Class III standards; demoisturization (bake-out) of the PWB for a minimum of 2 hours at 93°C ±5.5°C prior to soldering; ESD handling and control per established procedures; and use of clean, lint-free, anti-static gloves during assembly. All commercial parts require certificates of conformance, and passive component part numbers (resistors, capacitors, inductors) are subject to change based on market availability, provided that alternate parts meet or exceed original specifications and conform to the original form factor with system design engineer approval.

The PCB design includes primary (top layer) and secondary (bottom layer) configurations detailed on the assembly drawing, with component placement shown across multiple layers with various labeled elements (FB1-FB4 series, C series, U series, MH series, and others). The assembly must be completed in accordance with the referenced schematic (ADaPT GEN III Test PCB.PDF) and Altium control files (ADaPT GEN III Test PCB.ZIP). Final assemblies must be packaged in clean, static dissipative packaging, tagged with part and serial/lot numbers per SAE AS478 Method 35, and stored in a project-approved storage area. No changes beyond customary and standard assembly practices are permitted without prior written approval from NASA GRC. The document is marked as Preliminary and includes provisions for design review, approval signatures, and reference documentation including schematic drawings, PCB fabrication drawings, and bill of materials.

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Text version

A

A

B

B

C

C

D

D

E

E

F

F

1 1

2 2

3 3

4 4

5 5

6 6

J1

P1

FB3_25 FB3_26

FB1_26

FB3_27

FB1_27

FB3_28

FB1_28

FB3_29

FB1_29

FB3_30

FB1_30

FB3_31

FB1_31

FB3_32

FB1_32FB1_25

FB3_17 FB3_18

FB1_18

FB3_19

FB1_19

FB3_20

FB1_20

FB3_21

FB1_21

FB3_22

FB1_22

FB3_23

FB1_23

FB3_24

FB1_24FB1_17

FB3_9 FB3_10

FB1_10

FB3_11

FB1_11

FB3_12

FB1_12

FB3_13

FB1_13

FB3_14

FB1_14

FB3_15

FB1_15

FB3_16

FB1_16FB1_9

FB1_1 FB1_8

FB3_8

FB1_7

FB3_7

FB1_6

FB3_6

FB1_5

FB3_5

FB1_4

FB3_4

FB1_3

FB3_3

FB1_2

FB3_2FB3_1

FB

2_

FB

4_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

2_

FB

4_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

2_

FB

4_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

2_

FB

4_

FB

4_

FB

2_

J5 J4

C1_25

C2_25

C1 _2

C2 _2

C1_27

C2_27

C1_28

C2_28 C1_29

C2_29

C1_30C2_30

C1_31

C2_31

C1_32

C2_32

C1_17

C2_17

C1 _1

C2 _1

C1_19

C2_19

C1_20

C2_20 C1_21

C2_21

C1_22C2_22

C1_23

C2_23

C1_24

C2_24

C1_9

C2_9

C1 _1

C2 _1

C1_11

C2_11

C1_12

C2_12 C1_13

C2_13

C1_14C2_14

C1_15

C2_15

C1_16

C2_16

C

C

C2_8C1_8

C2_7C1_7

C2_6

C1_6

C2_5C1_5

C2_4

C1_4

C2_3

C1_3

C2 _2

C1 _2

C2_1

C1_1

R

R 7R

R5

R

R

R

R1

U1 _2

U1 _2

U1 _2

U1 _2

U1 _2

U1 _3

U1 _3

U1 _3

U1 _1

U1 _1

U1 _1

U1 _2

U1 _2

U1 _2

U1 _2

U1 _2

U1 _9

U1 _1

U1 _1

U1 _1

U1 _1

U1 _1

U1 _1

U1 _1

U1

_8

U1 _7

U1 _6

U1 _5

U1 _4

U1 _3

U1 _2

U1 _1

U 7 C

C

C

C

C

C 21C

C

C

C

C16 C15

C14C13

C

C11

C 10 C

C

C

C6

C

C

C

U 2_

U 3_

U 5_

U 6_

U 2_

U 3_

U 5_

U 6_

U 2_

U 3_

U 5_

U 6_

U

6U

U

U

U 4_

U

4_

U 4_

U

U12

C28

C

U10

U9

U11

U8

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M H

M

H

M H

M H

M H

M H

M H

M H

M

H

M H

M

H

J3

J2 J1

P1

View from Top side (Scale 5:2)

View from Bottom side (Scale 5:2)

CERTIFICATE OF CONFORMANCE REQUIRED FOR ALL COMMERCIAL PARTS.1.

ESD HANDLING AND CONTROL PER ESTABLISHED PROCEDURES.2.

HANDLE ALL PARTS AND ASSEMBLIES WITH CLEAN, LINT-FREE, ANTI-STATIC GLOVES OR FINGER COTS3.

DEMOISTURIZE (BAKE OUT) PWB FOR A MINIMUM OF 2 HOURS AT 93°C ±5.5°C (200°F ±10°F.) PERFORM SOLDERING IMMEDIATELY AFTER BAKING, OR STORE IN A CLEAN, DRY, SEALED STATIC DISSIPATIVE BAG OR CONTAINER.4.

MARK THE ASSEMBLY WITH P/N AND S/N USING WHITE EPOXY INK OR A LABEL.5.

ASSEMBLY, SOLDERING, AND INSPECTION SHALL BE IN ACCORDANCE WITH J‑STD‑001 CLASS III, IPC‑A‑610 CLASS III, PROCESS PLAN, AND THE FOLLOWING NOTES:

A. INSTALL AND SOLDER ALL SURFACE MOUNT (SMT) PART BEFORE THROUGH HOLE PARTS.

B. FOR THROUGH HOLE PARTS, LEAD TERMINATIONS SHALL BE STRAIGHT THROUGH (NOT LAPPED OR CLINCHED.)

C. PROCESS USING LEAD BASED, NO CLEAN SOLDER FORMULA

6.

PLACE THE COMPLETED ASSEMBLY IN CLEAN, STATIC DISSIPATIVE PACKAGING. IDENTIFY PART BY TAGGING WITH PART NUMBER AND SERIAL/LOT NUMBER AS SPECIFIED IN WORK ORDER PER SAE AS478, METHOD 35. STORE IN A PROJECT APPROVED STORAGE AREA.7.

REFERENCE SCHEMATIC: ADaPT GEN III Test PCB.PDF8.

ALTIUM CONTROL FILES: ADaPT GEN III Test PCB.ZIP9.

PASSIVE (RESISTORS, CAPACITORS, INDUCTORS) COMPONENT PART NUMBERS SUBJECT TO CHANGE BASED ON MARKET AVAILABILITY.

A. ANY ALTERNATE PARTS SELECTED WILL MEET OR EXCEED ORIGINAL SPECIFICATIONS

B. ANY ALTERNATE PARTS SELECTED WILL CONFORM WITH ORIGINAL PARTS' FORM FACTOR

C. SYSTEM DESIGN ENGINEER WILL APPROVE FINAL BILL OF MATERIALS.

10.

PRIMARY SIDE (TOP LAYER) AND SECONDARY SIDE (BOTTOM LAYER) SHOWN ON PAGE ONE OF THIS DOCUMENT.11.

NO CHANGES BEYOND CUSTOMARY AND STANDARD ASSEMBLY PRACTICES SHALL BE MADE WITHOUT PRIOR APPROVAL FROM NASA GRC.12.

=Scale

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DESIGN ITEM REVISION: DESIGN ITEM:

ADaPT GEN III PCB, Assembly Drawing.PCBDwf FILE NAME:

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=PCB_ENGINEER

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ENGINEER:

DATEAPPROVALS

=PCB_DWG_NO

=DOC_NO_SCH_DWG

=DOC_NO_FAB_DWG

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Reference Documents

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BOM DOC:

=PCB_ASSEMBLY_DRAWING_TITLE

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NASA Glenn Research Center 21000 Brookpark Rd Cleveland, OH 44135

Prel im ina ry

Prel im ina ry

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