Pod RAD _2_.pdf

AN/ALQ-184(V)

Requirements Allocation Document For the Pod Processors

Revision 05_9

Contract Number: Multiple

CDRL: N/A

June 21, 2006

Prepared by:

Raytheon

Space and Airborne Systems EW Operations

Goleta, CA 93117

Prepared for:

Department of the Air Force

WR-ALC/LSELP

Robins AFB, GA 31098

Distribution Statement D: Distribution authorized to DOD and DOD contractors only; (Critical Technology) (31 JUL 03). Other requests for this document or Questions concerning the technical content shall be referred to WR-ALC/LSELP, 380 Richard Ray Blvd Suite 104

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© 2005, Raytheon Systems Company, all rights reserved. This material may be reproduced by or for the U.S. Government pursuant to the copyright license under clause at DFARS 52.227-7013.

RAD-05

21 June 2006 ii

Revision History

Revision Date Pages Description Draft 4 May 2002 All 1) Re-typed Bob Loomis document

2) Corrected: A3A2A2AA9, TG Fault Logic PWA BIT MUX data B7 for

ECP98-01

Draft 15 May 2002 All 1) Re-typed Fred Lopez document

2) Added Register Hardware location information.

3) Corrected various names and data.

01 25 Jun 2002 All 1) Corrected A0F8 for run silent

(BCIII)

2) Added info to A0F4 02 24 Mar 2003 i, ii, 2 Added RWRI Reset- to Output Status

2 - A092 bit 6.

03 23 Nov 2003 i,ii, 22-31 Added TG RAD 04 24 Nov 2003 i, ii, 32-36 Added Low band RAD 05 1 Dec 2003 i, ii, 3, 10, 16 1) A092 corrected bits 1&2

2) Added pin numbers to A0CC, fixed bit 2

3) Added pin numbers to A0A8 05_1 26 Nov 2003 I,ii, 1) Change A0A8-b6

2) Added pin numbers to A090 05_2 9 Mar 2004 All

1) Fixed formatting

2) Fixed error in scaling of AGO

Calibration Data register.

3) Corrected error in Propeller Beam

Multiplex Sequence.

05_2 11 Mar 2004 Format changes 05_3 14 Apr 2004 4 1) Modified the AGO Calibration

Data register to show bit 0 unused with old scale.

05_4 16 Apr 2004 1) Added missing IO VCO, CIO …

2) Added IO Map Table iii

Revision History Revision Date Pages Description

05_5 24 June 2004 ii, 10, 15, 22, 23 1) Merge revision history and effective pages table

2) Corrected SCU Status description of BIT button

3) Changed LBF fault in BIT Register 3to RLBCPUOK-

4) Added description of SCU Button register bits.

5) Corrected Data Acq channels to include RHVPS changes

6) Better defined the Repeater/KO Beamport Registers

05_6 17 November 2004 24, 27 – 29 Deleted or repaired broken cross references. No changed in technical content.

05_7 16 May 2005 10 Fixed System Control Unit (SCU) Status (Input) A0F8 – A3A2A5A29U5 Control Unit ID sense

05_8 10 Nov 2005 39 Fixed paragraph 3.5 O_U1_STATUS

(READ) ADDRESS= 0X440000.

Added details about Short_pod bits and other bits specified as Spare, but used in LBPP and system.

05_9 21 June 2006 20 Updated paragraph 1.46 to correct details about TG interrupt signal iv

TABLE OF CONTENTS

Section Page

1. Pod System Processor

1.1 Receiver Detection Buffer – 0000:7000

1.2 Output Status 1 – A090 – A3A2A5A16U3

1.3 Output Status 2 – A092 – A3A2A5A14U5

1.4 AGO Fwd Beamport Select – A094

1.5 AGO Aft Beamport Select – A096

1.6 AGO Subband Calibration Select – A098

1.7 AGO Subband Calibration Data – A09A

1.8 Input Status - Receiver/Transmitter – A0F4 – A3A2A5A29U3

1.9 Receiver AOA Beamport Select Aft – AO9E –A3A2A5A16U5

1.10 Receiver AOA Beamport Select Fwd – AO9C – A3A2A5A16U5

1.11 PD/CW Status – MSB: A0FD LSB: A0F3

1.12 Receiver Subband ON/OFF Control – A0AE – A3A2A5A16U2

1.13 Noise Multiplex Buffer – A200 to A21E

1.14 Noise Multiplex Beamport Select

1.15 Multiplex Buffer Enable – A0AC – A3A2A5A16U8

1.16 Priority Threshold Control

1.17 VCO Setting and Calibration – Mid/High – 8600 – A3A2A5A27

1.18 Repeater/KO Beamport Select (OUTPUT) A0D0 to A0EE

1.19 System Control Unit (SCU) Status (Input) A0F8 – A3A2A5A29U5

1.20 SCU Button Status (Input) – A0FA – A3A2A5A29U6

1.21 SCU Button 8 (Output) – A0CC – A3A2A5A16U6

1.22 Priority Beamport Select – Fwd – A0A0 AFT – A0A2

1.23 Propeller Beam Multiplex Sequence – A260 to A26E A4A1A8U18&U19

1.24 Subband Technique Register – A0B0 – MA A3A2A5A17U1

1.25 Subband Technique Register – A0B2 – MB1 A3A2A5A17U2

1.26 Subband Technique Register – A0B4 – MB2 A3A2A5A17U3

1.27 Subband Technique Register – A0B6 – MB3 A3A2A5A17U4

1.28 Subband Technique Register – A0B8 – MC A3A2A5A17U5

1.29 Subband Technique Register – A0BA – HA A3A2A5A17U6

1.30 Subband Technique Register – A0BC – HB A3A2A5A17U7

1.31 Subband Technique Register – A0BE – HC A3A2A5A17U8

1.32 RWR Transmit Tag Register (184---RWR) – A0C4 A3A2A5A16U7

1.33 BIT Register 1 (Output) – A0A8 A3A2A5A14U6

1.34 BIT Register 2 (Output) – A0AA – A3A2A5A14U4

1.35 BIT Register 3 (Input) – A0F0 – A3A2A5A29U1

1.36 PIO Test Register (Output) – A0C0 – A3A2A5A16U1

1.37 PIO Test Register (Input) – A0F6 – A3A2A5A29U4

1.38 Low Band Address Strobe Register – Low Band Modification – A0C6

1.39 VCO Setting and Calibration – Low Band Modification

1.40 PD RAM - Subband Enable – A280 to A29E – A3A2A5A10U16

1.41 PD RAM – Hitcount, Pulse Width Enable – AnA0 to A2BE

1.42 Paged Memory Control – F600 – A3A2A5AA25

v

1.43 Channel 1 & 2 RS-232C – 8000 – A3A2A5A27

1.44 Channel 3 & 4 RS-232C – 8200 – A3A2A5A27

1.45 TG Serial Receiver Enable – 8400 – A3A2A5A27

1.46 TG Mux Strobe – F800 – A3A2A5A26U418

1.47 CIO – 9006 – A3A2A5A23

1.48 HVPS Controller

1.49 Data Acquisition – A3A2A5A20

1.49.1 Input Filters

1.49.2 Multiplexers

1.49.3 Scaling

1.49.4 A/D Conversion

1.49.5 Control

2. Techniques Generators

2.1 Fast Technique Generator RN2 Memory Mapped I/O Space

2.2 Fast Technique Generator RN2 port assignments

2.3 Fast technique generator V1 memory mapped I/0 space

2.4 Fast technique generator V1 Port assignments

2.5 Non-Standard Interface MUX memory mapped I/O space

2.6 Non-Standard Interface MUX PORT assignments

2.7 Standard Waveform Generator Memory Mapped I/O space

2.8 Standard Waveform Generator PORT assignments

3. Low Band

3.1 Reserved Low Addresses

3.2 IO_NET_WR_RST (Write) Address = 0x420000

3.3 IO_NET_RD (Read) ADDRESS = 0x430000

3.4 IO_NET_WR (Write) ADDRESS = 0x430000

3.5 IO_U1_STATUS (Read) ADDRESS= 0x440000

3.6 IO_BIT_STATUS (Read) ADDRESS=0x440010

3.7 IO_U1_ECHO_INPUT (Read) Address=0x440020

3.8 IO_9492_CIU_STATUS (Read) Address= 0x460000

3.9 IO_MOD_BIT (Read) Address=0x470000

3.10 IO_SYSTEM_CONTROL (Write) Address=0x450010

3.11 IO_U1_ECHO_OUTPUT (Write) Address=0x450020

3.12 IO_DITHER_RATE (Write) Address= 0x450030

3.13 IO_MODULATION_RATE (Write) Address= 0x480000

3.14 IO_MODULATION_RATE_SYNC (Write) Address=0x480008

3.15 IO_DMA_ADDRESS (Write) Address= 0x490000

3.16 IO_DMA_TO_TGT_MAP (Write) Address= 0x4A0000

3.17 IO_MODULATION_CONTROL (Write) Address = 0x4B0000

3.18 High Addresses

3.19 Revisions

vi

LIST OF TABLES

Table Page

Table 1 New Data Acquisition Channels Table 2 Data Acquisition Channels Table 3 Interface Description Table 4 I/O Memory Space Map

1. POD SYSTEM PROCESSOR

1.1 RECEIVER DETECTION BUFFER – 0000:7000

The data in the buffer shall consist of the number of threshold crossings within a 100 msec period. The buffer shall consist of two 1024 x 8 scratch pad memories that alternate in a “ping pong” manner to allow uninterrupted recording of crossings, while the data is accessed by the microprocessor. The Pod System Processor shall clear its side of the buffer before it turns it over to the receiver. The data within the detection buffers shall be organized by subband, sector, the AOA.

The following is a diagram of the buffer organization:

B9 B8 B7 B6 B5 B4 B3 B0

SUBBAND SEC AOA

multi threat prio rity

B7 B6 B5 B4 B3 B2 B1 B0

MA 0 0 0 0=FWD 0 0 0 0

MB1 0 0 1 1=AFT 0 0 0 1-

MB2 0 1 0 .

MB3 0 1 1 .

MC 1 0 0 .

HA 1 0 1

HB 1 1 0

HC 1 1 1 1 0 0 0-

1 0 0 1- 1 1 1 1-

[--------------8 Bits--------------]

DATA UP TO 255 COUNTS

Uncorrelated AOA

Primary Beams

Combination Beams

The following I/O address mode for the receiver detection buffer is outlined below. The data is retrieved through an I/O word mapped word read.

1.2 OUTPUT STATUS 1 – A090 – A3A2A5A16U3

B7 B6 B5 B4 B3 B2 B1 B0 Bit 05 64 65 45 16 63 62 35 Pin

M/HAH+ M/HAM+ HCOVR+ M/HPH+ M/HPM+ TCEN+ Spare NZACT+ Signal

B0 = Noise Active + (0 = Off 1 = Active) B1 = Spare B2 = Activate Multi-Threat Processing + B3 = Priority Beam Active + Mid Band (XMIT) B4 = Priority Beam Active + High Band (XMIT) B5 = KO VCO Enable- (0 = Enable HC HIGH 1 = OFF) B6 = AGO Calibration Enable +, Mid Band B7 = AGO Calibration Enable +, High Band

Address Bit/

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Definition

0 0 0 0 0 ------------------------------- 0 Reset Test Control BIT (0000)16

0 0 0 1 0 ------------------------------- 0 Set Test Control Bit (1000)16

0 0 1 0 0 ---Address--------------------- 0 Test Receiver Strobe (2xxx)16

0 0 1 1 0 ------------------------------- 0 Spare

0 1 0 0 0 ---Address--------------------- 0 Read and Clear Buffer (4xxx)16

0 1 0 0 1 ---Address--------------------- 0 Read Addressed Buffer (4xxx)16

0 1 0 1 0 ------------------------------- 0 Select Buffer “A” (5000)16

0 1 1 0 0 ------------------------------- 0 Select Buffer “B” (6000)16

0 1 1 1 0 ------------------------------- 0 Toggle Buffers (7000)16

1.3 OUTPUT STATUS 2 – A092 – A3A2A5A14U5

78 76 47 81 80 51 79 18 Pin

MRST- RWRRS- CVRRS+ LORWR+ RWRON+ HIDTY- LODTY- DU1+ Signal

B0 = Special Noise Active + (0 = Inactive 1 = Active) B1 = Spare B2 = Spare

B3 = RWR LTB ON/OFF +

B4 = Low Band RWR ON/OFF + B5 = AGO CVR RESET + (0 = Inactive 1 = Active) B6 = RWRI – Reset (BCIII) B7 = TG Reset- (0 - Reset, 1 = Inactive)

1.4 AGO FWD BEAMPORT SELECT – A094

Register 1 Fwd AGO Beamport Select – A094

B7 B6 B5 B4 B3 B2 B1 B0 BIT

8 7 6 5 4 3 2 1 Beam No.

1.5 AGO AFT BEAMPORT SELECT – A096

Register 2 Aft AGO Beamport Select – A096

B7 B6 B5 B4 B3 B2 B1 B0 BIT

8 7 6 5 4 3 2 1 Beam No.

1.6 AGO SUBBAND CALIBRATION SELECT – A098

AGO Sub-band Select – A098

HC HB HA MC MB3 MB2 MB1 MA

1.7 AGO SUBBAND CALIBRATION DATA – A09A

AGO Sub-band Data – A09A

UNUSED

B7-B1 = Digital value to obtain 0 to 10v range on DAC for 0-60 dB of attenuation in

1.33 dB increments

1.8 INPUT STATUS - RECEIVER/TRANSMITTER – A0F4 – A3A2A5A29U3

Input Status – Receiver/Transmitter – A0F4 – A3A2A5A29U3

32 34 36 37 70 35 33 67

ADRDY+ RLB_DONE Spare 28VUP- HBRP+ MCRP+ MB1RP+ AGO0+

B0 = AGO Cal CW Indicate + (0 ≠ CW, 1 = CW) B1 = R/N 1 (0 = Noise, 1 = Repeater) MB1 Subband B2 = R/N 2 (0 = Noise, 1 = Repeater) MC Subband B3 = R/N 3 (0 = Noise, 1 = Repeater) HB Subband B4 = Delay 28v Status + (200/10 sec timeout)

0 = Not Active (No Warmup) 1 = Active (Warmup) B5 = Not Used (256K Dense Memory ID) MEMHVID- B6 = RLB_Done – (0 = RLB not loaded; 1 = RLB XLINX load complete) B7 = Analog to Digital Conversion Ready +

1.9 RECEIVER AOA BEAMPORT SELECT AFT – AO9E –A3A2A5A16U5

Register 1 AOA Beamport Select Aft – A09E

8 7 6 5 4 3 2 1

Primary Beam 1 = 0000 0001 Intermediate Beam 1 = 0000 0011 Primary Beam 2 = 0000 0010 Intermediate Beam 2 = 0000 0110 Primary Beam 3 = 0000 0100 Intermediate Beam 3 = 0000 1100 Primary Beam 4 = 0000 1000 Intermediate Beam 4 = 0001 1000 Primary Beam 5 = 0001 0000 Intermediate Beam 5 = 0011 0000 Primary Beam 6 = 0010 0000 Intermediate Beam 6 = 0000 0110 Primary Beam 7 = 0100 0000 Intermediate Beam 7 = 1100 0000 Primary Beam 8 = 1000 0000

1.10 RECEIVER AOA BEAMPORT SELECT FWD – AO9C – A3A2A5A16U5

Register 2 AOA Beamport Select Fwd – A09C

Primary Beam 1 = 0000 0001 Intermediate Beam 1 = 0000 0011 Primary Beam 2 = 0000 0010 Intermediate Beam 2 = 0000 0110 Primary Beam 3 = 0000 0100 Intermediate Beam 3 = 0000 1100 Primary Beam 4 = 0000 1000 Intermediate Beam 4 = 0001 1000 Primary Beam 5 = 0001 0000 Intermediate Beam 5 = 0011 0000 Primary Beam 6 = 0010 0000 Intermediate Beam 6 = 0000 0110 Primary Beam 7 = 0100 0000 Intermediate Beam 7 = 1100 0000 Primary Beam 8 = 1000 0000

1.11 PD/CW STATUS – MSB: A0FD LSB: A0F3

B15 B8 B7 B0

0 = No PD/CW 1 = PD/CW Present

1.12 RECEIVER SUBBAND ON/OFF CONTROL – A0AE – A3A2A5A16U2

Receiver Subband ON/OFF Control – A0AE

06 69 71 73 72 67 66 38 Pin

HC HB HA MC MB3 MB2 MB1 MA S/B

HCON+ HBON+ HAON+ MCON+ MB3ON+ MB2ON+ MB1ON+ MAON+ Sin

1 = ON, 0 = OFF

1.13 NOISE MULTIPLEX BUFFER – A200 TO A21E

Mid/ SUBBAND High Spare Spare EOS LTN

Mid/High 0 = Mid 1 = High

EOS

0 = EOS

1 = EOS

LT/NOISE (LTN)

0 = Noise 1 = Lookthru

Subband

000 = MA

001 = MB1

010 = MB2

011 = MB3

100 = MC

101 = HA

110 = HB

111 = HC

1.14 NOISE MULTIPLEX BEAMPORT SELECT

Fwd = A220 to A23E Aft = A240 to A25E

Fwd: A220 to A23E

Aft: A240 to A25E

1.15 MULTIPLEX BUFFER ENABLE – A0AC – A3A2A5A16U8

1.16 PRIORITY THRESHOLD CONTROL

Select = A0A4 Data = A0A6

A0A4 – Select

A0A6 – Data

B7 B5 B5 B4 B3 B2 B1 B0

Data LSB = 39mv Conversion = 80mv/dB

Multiplex Buffer Enable – A0AC

49 24 25 58 29 18 48 19

Spare RLB_

DIN

RLB_

SYNC

RLB_

CCLK

RLB_

RESET-

AREN+ HDEN+ CWMXN+

B0 = Propeller Mux enable

1 = enable

0 = disable

B1 = Noise Mux enable 1 = enable 0 = disable B2 = Pulse Doppler Mux enable 1 = enable 0 = disable B3 = RLB_RESET- 1 = enable 0 = disable B4 = RLB_CCLK Indicate RLB LBPP or Mission B5 = RLB_SYNC Signal used to indicate 32 bit word to be sent to LBP B6 = RLB_DIN RLB discrete data line B7 = Spare

1.17 VCO SETTING AND CALIBRATION – MID/HIGH – 8600 – A3A2A5A27

The serial data associated with each command type is clocked out of the two upper bits (B7-

6) of the VCO Command Register.

Command Data Dec Hex Description Serial Data Word Type

0 0 Clear Shift register N/A 1 1 VCO 1 MA FG VCO Frequency tune 2 2 VCO 2 MA BG VCO Frequency tune 3 3 VCO 3 MB1 FG VCO Frequency tune 4 4 VCO 4 MB1 BG VCO Frequency tune 5 5 VCO 5 MB2 FG VCO Frequency tune 6 6 VCO 6 MC FG VCO Frequency tune 7 7 VCO 7 MC BG VCO Frequency tune 8 8 VCO 8 HB FG VCO Frequency tune 9 9 VCO 9 KO Local oscillator VCO Frequency tune

10 A VCO 10 HC FG VCO Frequency tune 11 B Not used 12 C Not used 13 D Not used

14 E Modulation sensitivity.

0 = 50MHz/V 1 = 250MHz/V

VCO Set

15 F VCO command

0 = OFF

1 = ON

VCO Set

VCO Frequency Tune Word (Serial Data)

B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

VCO Set Word (Serial Data)

B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

HCF HCKO HBF MCB MCF MB2F MB1B MB1F MAB MAF

VCO # Name VCO # Name

1 MAF (MA FG) 6 MCF (MC FG)

2 MAB (MA BG) 7 MCB (MC BG)

3 MB1F (MB1 FG) 8 HBF (HB FG)

4 MB1B (MB1 BG) 9 HCKO (KOVCO)

5 MB2F (MB1 FG) 10 HCF (HCFG)

8600 – VCO Command Register B7 B6 B5 B4 B3 B2 B1 B0

SER

DATA

SER

CLK

COMMAND DATA

1.18 REPEATER/KO BEAMPORT SELECT (OUTPUT) A0D0 TO A0EE

This is the part of the hardware control for the Latch Correlator on boards A4A1A7, A8, ,A10, and A11.

ADDR B7 B6 B5 B4 B3 B2 B1 B0

X 8 7 6 5 4 3 2 1 Forward

X+0x10 8 7 6 5 4 3 2 1 Aft

A0D0 Beamport Select Fwd. - MA A0D2 Beamport Select Fwd. - MB1 A0D4 Beamport Select Fwd. - MB2 A0D6 Beamport Select Fwd. - MB3 A0D8 Beamport Select Fwd. - MC A0DA Beamport Select Fwd. - HA A0DC Beamport Select Fwd. - HB A0DE Beamport Select Fwd. - HC A0E0 Beamport Select Aft. - MA A0E2 Beamport Select Aft. - MB1 A0E4 Beamport Select Aft. - MB2 A0E6 Beamport Select Aft. - MB3 A0E8 Beamport Select Aft. - MC A0EA Beamport Select Aft. - HA A0EC Beamport Select Aft. - HB A0EE Beamport Select Aft. – HC

1.19 SYSTEM CONTROL UNIT (SCU) STATUS (INPUT) A0F8 – A3A2A5A29U5

This was modified by the RLB upgrade to remove the C-6631 as an option as a control unit for the pod.

C9492 SCU – A0F8

78 77 16 76 75 14 74 73 B7 B6 B5 B4 B3 B2 B1 B0

CUID+ RUN_SILENT- SVBIT+ OPER+ STBY+ XMTS3- XMTS2- XMTS1-

B0 = XMIT 1 switch position.

0 = On

1 = Off

B1 = XMIT 2 switch position. 0 = On 1 = Off B2 = XMIT 3 switch position. 0 = On 1 = Off B3 = OFF/STBY/OPER switch. 0 = Off/OPER 1 = STBY B4 = XMIT 1 or XMIT 2 or XMIT 3 ON 0 = false 1 = true B5 = BIT pushbutton switch. 0 = Active (depressed) 1 = Inactive (released) B6 = RUN_SILENT- 0 = On 1 = Off B7 = Control Unit ID. 0 = C9492 1 = Illegal (6631/Analog)

1.20 SCU BUTTON STATUS (INPUT) – A0FA – A3A2A5A29U6

A0FA - Button Status

S8 S7 S6 S5 S4 S3 S2 S1

B0 = S1 Button position 0 = On (depressed) 1 = Off (released) B1 = S2 Button position 0 = On (depressed) 1 = Off (released) B2 = S3 Button position 0 = On (depressed) 1 = Off (released) B3 = S4 Button position 0 = On (depressed) 1 = Off (released) B4 = S5 Button position 0 = On (depressed) 1 = Off (released) B5 = S6 Button position 0 = On (depressed) 1 = Off (released) B6 = S7 Button position 0 = On (depressed) 1 = Off (released) B7 = S8 Button position 0 = On (depressed) 1 = Off (released)

1.21 SCU BUTTON 8 (OUTPUT) – A0CC – A3A2A5A16U6

C9492 Pushbutton Lamp Status – A0CC 51 79 81 84 83 80 78 21 B7 B6 B5 B4 B3 B2 B1 B0

Spare Spare Spare High Band Fault Lamp

Mid Band Fault Lamp ALFLT+ ULL+ STBY

B0 = Button 8 Upper Right Lamp 0 = not in standby lamp OFF 1 = Standby lamp ON B1 = Button Upper Left Lamps 0 = lamps OFF 1 = lamps ON B2 = Button 8 Lower Left Lamp 0 = lamp OFF no low band fault.

1 = lamp ON low band fault B3 = Button 8 Lamp 0 = lamp OFF no mid band and fwd transmitter fault 1 = lamp ON mid band and/or fwd transmitter fault B4 = Button 8 Lamp 0 = lamp OFF no high band and aft transmitter fault 1 = lamp ON high band and/or aft transmitter fault B5-B7 = Spare

1.22 PRIORITY BEAMPORT SELECT – FWD – A0A0 AFT – A0A2

Register 1 FWD – A0A0 Register 2 AFT – A0A2

B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

Primary beams. To select intermediate beams use the two adjacent primary beams. For example 0000 0011 is an intermediate beam that lies spatially between the two primary beams, 1 and 2.

1.23 PROPELLER BEAM MULTIPLEX SEQUENCE – A260 TO A26E

A4A1A8U18&U19

An eight-entry sequence is used for all subbands. Only one sequence is programmed for both forward and aft propeller beam sequences.

A260 to A26E

The RAM chips U18 and U19 on latch correlator A4A1A8 will hold 16x8 bits. However only 8x8bits are addressable by the multiplex clocking signals.

Propeller Beam Mux Select A260 – A26E

1.24 SUBBAND TECHNIQUE REGISTER – A0B0 – MA A3A2A5A17U1

Subband Technique Register A0B0 MA

Spare Spare MAXPN+ MACWP+ MAPRN+ Spare PR

B0 = Not used B1 = Priority – not a hardware bit B2 = Not Used B3 = AOT mode control – repeater programmed B4 = AOT mode control – CW programmed B5 = AOT mode control – noise programmed B6 = Not used B7 = Not used

1.25 SUBBAND TECHNIQUE REGISTER – A0B2 – MB1 A3A2A5A17U2

Subband Technique Register A0B2 MB1

A9/A5 Spare M1XPN+ M1CWP+ M1PRN+ MB1KN+ PR Spare

B0 = Not used B1 = Priority – not a hardware bit B2 = AOT mode control – KO programmed B3 = AOT mode control – repeater programmed B4 = AOT mode control – CW programmed B5 = AOT mode control – noise programmed

B7 = A9 or A5 technique – not a hardware bit

1.26 SUBBAND TECHNIQUE REGISTER – A0B4 – MB2 A3A2A5A17U3

Subband Technique Register A0B4 MB2

Spare Spare M2XPN+ M2CWP+ M2PRN+ Spare PR Spare

B0 = Not used B1 = Priority – not a hardware bit B2 = Not Used B3 = AOT mode control – repeater programmed B4 = AOT mode control – CW programmed B5 = AOT mode control – noise programmed

1.27 SUBBAND TECHNIQUE REGISTER – A0B6 – MB3 A3A2A5A17U4

Subband Technique Register A0B6 MB3

M3XPN+ M3CWP+ M3PRN+ PR

B0 = Not used B1 = Priority – not a hardware bit B2 = Not Used B3 = AOT mode control – repeater programmed B4 = AOT mode control – CW programmed B5 = AOT mode control – noise programmed

1.28 SUBBAND TECHNIQUE REGISTER – A0B8 – MC A3A2A5A17U5

Subband Technique Register A0B8 MC

A9/A5 Spare MCXPN+ MCCWP+ MCPRN+ MCKN+ PR Spare

B0 = Not used B1 = Priority – not a hardware bit B2 = AOT mode control – KO programmed B3 = AOT mode control – repeater programmed B4 = AOT mode control – CW programmed B5 = AOT mode control – noise programmed

1.29 SUBBAND TECHNIQUE REGISTER – A0BA – HA A3A2A5A17U6

Subband Technique Register A0BA HA

Spare Spare HAXPN+ HACWP+ HAPRN+ Spare PR Spare

B0 = Not used B1 = Priority – not a hardware bit B2 = Not used B3 = AOT mode control – repeater programmed B4 = AOT mode control – CW programmed B5 = AOT mode control – noise programmed

1.30 SUBBAND TECHNIQUE REGISTER – A0BC – HB A3A2A5A17U7

Subband Technique Register A0BC HB

A9/A5 HBXPN+ HBCWP+ HBPRN+ HBKN+ PR Spare

B0 = Not used B1 = Priority – not a hardware bit B2 = AOT mode control – KO programmed B3 = AOT mode control – repeater programmed B4 = AOT mode control – CW programmed B5 = AOT mode control – noise programmed B6 = select the quadrature modulator on the RF deck

1.31 SUBBAND TECHNIQUE REGISTER – A0BE – HC A3A2A5A17U8

Subband Technique Register A0BE HC

A9/A5 HCSSM+ HCXPN+ HCCWP+ HCPRN+ HCKN+ PR Spare

B0 = Not used B1 = Priority – not a hardware bit B2 = AOT mode control – KO programmed B3 = AOT mode control – repeater programmed B4 = AOT mode control – CW programmed B5 = AOT mode control – noise programmed B6 = Selects the quadrature modulator on the RF deck

1.32 RWR TRANSMIT TAG REGISTER (184---RWR) – A0C4 A3A2A5A16U7

Selects the subband that will send a transmit tag to the RWR Interface for the duration of transmission in the selected subband.

RWR Transmit Tag Register A0C4

1.33 BIT REGISTER 1 (OUTPUT) – A0A8 A3A2A5A14U6

This controls the setup of the three BIT switches that control signal routing for BIT testing, external test point A3A1TP1. The actual signal names going to the test switches is shown in BIT Register 1 table. The following table is provided to tie the test switches to the hardware nomenclature:

Ref Design Switch Purpose A3A2S1 Test Switch 1 Routes signal to the receiver inputs A3A1A5S9 Test Switch 2 Routes signal from the mid or high band channelizer A3A1A5S10 Test Switch 3 Routes signal from fwd or aft Xmit lens output

BIT Register 1 – A0A8

35 38 40 52 89 69 07 36 B7 B6 B5 B4 B3 B2 B1 B0

Spare KOTST+ TST3B+ TST3A+ TST2B+ TST2A+ ART1B+ ART1A+

B0 = Test switch selects the fwd/mid band receive lens coupler injection port B1 = Test switch selects the aft/high band receive lens coupler injection port B2 = Test switch selects the high band channelizer coupled output B3 = Test switch selects the mid band channelizer coupled output B4 = Test switch selects the fwd transmit lens coupler output port B5 = Test switch selects the aft transmit lens coupler output port B6 = KOTST+ not used since (V)5

1.34 BIT REGISTER 2 (OUTPUT) – A0AA – A3A2A5A14U4

BIT Register 2 – A0AA

RSCTL2 RSCTL1 V9DIEN ARBIT+ Spare Spare BBDS2+ BBDS1+

B0 =Minor fault bit ball 0=no fault 1=fault B1 = Major fault bit ball 0=no fault 1=fault B2 = Spare B3 = Spare B4 = Auxiliary receiver BIT enable 0=disable 1=enable B5 = VCO 9 0=disable 1=enable B6 = Control 1 for AGO switch See truth table below B7 = Control 2 for AGO switch See truth table below

AGO CVR Switch Logic

Input Output

RSCTL1 RSCTL2 RSWEN-

1 0 CVR Switch off 1 1 CVR Switch on/off at a 1MHz rate

1.35 BIT REGISTER 3 (INPUT) – A0F0 – A3A2A5A29U1

BIT Register 3 – A0F0

PU+ LTBEN+ RLBCPUOK- BIT+ CPGF+ RLB- 50KOK- 3MOK-

B0 = 3MHz BIT 0=no fault 1=fault B1 = 50KHz BIT 0=no fault 1=fault B2 = RLB pod 0= RLB pod 1= non-RLB pod B3 = Complex Waveform Generator (white noise to VCOs) 0=no fault 1=fault B4 = TG BIT 0=fault 1=no fault B5 = Low CPU OK Fault 0=no fault 1=fault B6 = RWR Look-though/Blanking enable 0=disable 1=enable B7 = RF Integration. Not used currently pulled up to a logical 1. Available for new design

1.36 PIO TEST REGISTER (OUTPUT) – A0C0 – A3A2A5A16U1

All eight (TSPTx+) signals are wrapped around from the A3A2A5A16 to A3A2A5A26U4 (A0F6) to test the PIO. The signals are also sent to the auxiliary receiver processor A3A2A5A10U8 BIT test Mux to be decoded as shown below.

PIO Test Register – A0C0

Input Select Test Sw 1B select Test Sw 1A select Clock

TSPT8+ TSPT7+ TSPT6+ TSPT5+ TSPT4+ TSPT3+ TSPT2+ TSPT1+

B0 = Auxiliary rcvr Clock Select. 0= 100KHz, 1= 1MHz B1-B2 = A3A2S1 Test Switch 1A control fwd/mid. See truth table ART1A+.

B3-B4 = A3A2S1 Test Switch 1 ART1B+ control aft/high. See truth table ART1B+.

B5-B7 = Auxiliary rcvr input control. See truth table Input Select.

Test Switch 1A Logic

TSPT2+ TSPT3+ ART1A+

0 0 Switch off 0 1 1MHz chop 1 0 Clock/128 1 1 Under PSP control

Test Switch 1B Logic Input Output

TSPT2+ TSPT3+ ART1B+

0 0 Switch off 0 1 1MHz chop 1 0 Clock/128 1 1 Under PSP control

Input Select Logic

TSPT8+ TSPT7+ TSPT6+

0 0 0 DETCVR

0 0 1 FSCMXSB+

0 1 0 ARINB+

0 1 1 Spare 1 0 0 Clock/128

1 0 1 ASCMXSB+

1 1 0 AGOIB+

1 1 1 Spare

1.37 PIO TEST REGISTER (INPUT) – A0F6 – A3A2A5A29U4

This register receives the PIO signals from A0C0 (A3A2A5A16U1) as an echo test.

PIO Test Register –A0F6 B7 B6 B5 B4 B3 B2 B1 B0

TSPT8+ TSPT7+ TSPT6+ TSPT5+ TSPT4+ TSPT3+ TSPT2+ TSPT1+

1.38 LOW BAND ADDRESS STROBE REGISTER – LOW BAND

MODIFICATION – A0C6

This modification was never fielded and the register has no function.

1.39 VCO SETTING AND CALIBRATION – LOW BAND MODIFICATION

This modification was never fielded and the register has no function.

1.40 PD RAM - SUBBAND ENABLE – A280 TO A29E – A3A2A5A10U16

Sixteen Subband Ram positions are available: A280, A282, A284, A286, A288, A28A, A28C, A28E, A290, A292, A294, A296, A298, A29A, A29C, A29E.

PD RAM – Subband Select

Spare OKF THS NRF EOS Subband

B0-B2 = Subband Select 000=MA (null) 111=HC B3 = End Of Sequence B4 = Noise Rejection Flag 0= disable 1= enable B5 = Threshold Select 0= Noise 1= fixed voltage B6 = 100KHz Filter Flag 0=CW (100KHz) 1=NRF or pulse (4MHz)

1.41 PD RAM – HITCOUNT, PULSE WIDTH ENABLE – ANA0 TO A2BE

Sixteen Ram positions are available: A2A0, A2A2, A2A4, A2A6, A2A8, A2AA, A2AC, A2AE, A2B0, A2B2, A2B4, A2B6, A2B8, A2BA, A2BC, and A2BE.

PD RAM – Hit count & Pulse Width Enable

Min. Hit Count threshold per 620μS period Minimum Pulse Width in μS

Bit Pattern Hit Count Pulse Width 0000 Off Off 0001 2 0.166 0010 4 0.250 0011 8 0.333 0100 16 0.500 0101 32 0.667 0110 64 0.750 0111 96 0.833 1000 128 1.000 1001 160 1.500

Bit Pattern Hit Count Pulse Width 1010 192 2.000 1011 224 4.000 1100 256 6.000 1101 Spare 8.000 1110 Spare 10.00

1111 CW 13.00

1.42 PAGED MEMORY CONTROL – F600 – A3A2A5AA25

The Paged Memory Control modifies the memory page mapped to the upper 32 Kbytes of the PSPP memory address space. The lower 32 Kbytes are always mapped to global RAM.

Paged Memory Control – F600

Spare Spare Spare Spare Spare Page Select

Page Selection

Bit pattern Selection Mem Type 000 Page 0 EEPROM 001 Page 1 EEPROM 010 Page 2 EEPROM 011 Page 3 EEPROM 100 Page 4 EEPROM 101 Page 5 EEPROM 110 Page 6 RAM

1.43 CHANNEL 1 & 2 RS-232C – 8000 – A3A2A5A27

Channels 1 &2 are implemented with a Zilog Z8530 Serial Communications Controller (SCC) chip U6 that is located at base address 0x8000.

Channel 1 (A on Z8530 U6) MLV/ASE Channel 2 (B on Z8530 U6) LBPP (RLB) Interface

1.44 CHANNEL 3 & 4 RS-232C – 8200 – A3A2A5A27

Channels 3 & 4 are implemented with a Zilog Z8530 Serial Communications Controller (SCC) chip U7 that is located at base address 0x8200.

Channel 3 (A on Z8530 U7) RWR Interface Channel 4 (B on Z8530 U7) TG Data

1.45 TG SERIAL RECEIVER ENABLE – 8400 – A3A2A5A27

This register is used to enable the addressed TG to receive an outgoing serial message from serial channel 4.

A3A2A5A27 U4

TG Address Unused TG Data Strobe

MPSA3 MPSA2 MPSA1 MPSA0 --- --- --- MPST2-

B0 = MPST2 – TG serial data output strobe, 0=Enable, 1=Disable B1-B3 = Unused B4-B7 = MPSA0-MPSA3, TG Address 4=RN TG, 15=HC Std.

1.46 TG MUX STROBE – F800 – A3A2A5A26U418

Outputting any data to this address will strobe a TG interrupt on signal MPST1-. This signal is generates on the Program Control PWA (A3A2A5A26) U4 pin 18.

1.47 CIO – 9006 – A3A2A5A23

Counter/Timer Parallel IO Unit - Z8536 CIO chip. Port B is the real time clock.

CIO Port A: Data Input (HVPSC), Interrupt Address D16)

CIO Port B: (Interrupt Address E16)

Spare INFP- LSD- CRAS

E-

GDI- HVON

C-

CLOF

F-

CTOF

F-

CIO Port C: (Interrupt Address Flag F16)

HVPSC

B3 B0

RFD+ DAV- Spare SRQ-

1.48 HVPS CONTROLLER

The new PWA will process the fault lamp indications and provide a +5V fail-safe override in the same manner as the existing PWAs. These controls replace the previous CI/O communication path to the Z8 on the HVPS controller PWA.

Table 1 New Data Acquisition Channels

Minor Fault Major Fault Turn Off Logical CH # Description Lo Hi Lo Hi Lo Hi

0 FWD HTR VOLT 5.85 6.75 5.85 6.75 5.85 N/A

1 FWD COLL VOLT 3.685 4.529 3.116 5.704 N/A 5.704

2 FWD CATH VOLT 7.624 7.976 7.446 8.036 7.446 8.036

9 FWD COLL CURR 6.840 10.08 5.985 11.50 N/A 11.50

10 AFT HTR VOLT 5.85 6.75 5.85 6.75 5.85 N/A

14 AFT COLL VOLT 3.685 4.529 3.116 5.704 N/A 5.704

16 AFT CATH VOLT 7.624 7.976 7.446 8.036 7.446 8.036

17 AFT COLL CURR 6.840 10.08 5.985 11.50 N/A 11.50

NOTE: CH 1, 2, 14 and 16 are magnitudes on production supplies, they are negative voltages while 5 Lot are positive.

Address Data Data Description

9600 B7-B0 Digital value for FWD gross helix trip point:

LSB = 0.39V

Trip point > 2.016V

9602 B7-B0 Digital value for FWD TWT status trip point:

LSB = 0.39V

Trip point < 4.5V 9604 B7-B0 FWD HVPS Relay/TWT Enable

Enable = 0 Disable = 1 Data B7 B6 B5 B4 B3 B2 V1 B0

TWT V8 V7 V6 V5 V4 V3 V2 V1

Relay K4 K3 K2 K1 K8 K7 K6 K5

9606 B7-B0 AFT HVPS Relay/TWT Enable:

Same description as above except TWTs under control are V16-V9 instead of V8-V1

9608 B3, B2 HVPS ON/OFF Command:

Off = 1

On = 0

Address Data Data Description

B3 = FWD HVPS

B2 = AFT HVPS

9610 B7-B0 Digital value for AFT gross helix trip point:

LSB = 0.39V

Trip point > 2.016V

9612 B7-B0 Digital value for AFT gross helix trip point:

LSB = 0.39V

Trip point < 4.5V

960A B7-B4

Circuit Breaker Status (moved from Data ACQ):

B7 = CB1

C6 = CB3

B5 = CB4

B4 = CB5

Fault status handled same as unmodified S/W

B3-B2

HVPS Overtemp Sensor:

Overtemp = 0 Ok = 1

B3 = FWD

B2 = AFT

Overtemp is major fault

B1-B0

Gross Helix Status:

Fail = 1 Ok = 0

B1 = FWD

B0 = AFT

Fail is major fault

960C B7-B0

FWD HVPS Relay/TWT:

Status Fail = 0 Ok = 1

B7-B0=V8-V1=K4=K1, K8-K5 Minor fault = 1 of 8 fail Major fault = 2 or more of 8 fail

960E B7-B0

AFT HVPS Relay/TWT:

Status Fail = 0 Ok = 1 Same description as above except TWT status is for V16-V9 instead of V8-V1

1.49 DATA ACQUISITION – A3A2A5A20

The Data Acquisition board performs analog-to-digital conversion on 32 analog channels. As designed, 24 channels have a maximum input voltage range of ± 10V and eight channels have a maximum input voltage range of ± 20V. Within these ranges the actual channel scale factors are software selectable. The analog inputs are filtered, multiplexed, scaled, and then digitized.

1.49.1 Input Filters

Input filters are single pole (R-C) low pass filters with a cutoff frequency of approximately 30 Hz. For the eight ± 20V channels, resistive dividers (matched to 0.1%) reduce the input voltages ± 10V.

1.49.2 Multiplexers

Four eight-channel analog multiplexers select one of the 32 channels to be digitized. For testability purposes, the outputs of the multiplexers are brought out to the card edge connector, and are jumpered together off the card. A precision op-amp is used to buffer the multiplexed output. The JFET multiplexers used do not exhibit the static discharge blow out problem associated with CMOS devices.

1.49.3 Scaling

Scaling of the analog inputs is done with a 10-bit multiplying DAC. A scale factor is loaded from the processor data bus at the same time that a channel is selected for conversion. Use of the DAC allows the data normalization and preserves resolution on lower voltage channels. Any input voltage between 2.5V and 10V can be scaled to half-scale on the A/D output (5.0V and 20V for the 20 volt channels). The gain of the DAC and A/D converter and the offset of the A/D converter are trimmed with select in test resistors on the DAC output amplifier.

1.49.4 A/D Conversion

An Analog Device 570AD eight-bit A/D performs the analog-to-digital conversion function.

Conversion time is 30 microseconds. A 54LS240 octal buffer interfaces the digital output to the processor data bus.

1.49.5 Control

Control of the Data Acquisition board occupies two contiguous word locations in the system I/O space, as determined by the Address Decoder PWA. A conversion sequence is performed as follows.

First, a write is performed to the first memory location. The lowest five bits of the word written specifies the channel and highest ten bits specify the scale factor. After allowing a minimum of 3 microseconds of setting time, a write is performed to the second location, which starts a conversion. When the conversion is complete, the ADRDY+ bit in Bit 7 of Input Status Register goes high. The processor performs a read of the first memory location, which places the A/D output on the processor data bus. The converted value read is 8-bit offset binary and is read on data lines D07-D00. Values represented in offset binary can be converted to 2’s complement representation by complementing the MSB.

The sale factor is a 10-bit unsigned binary number with 11 111 1111 giving a scale factor of 1023/1024, 000000 0000 giving 0/1024, 00 0000 0001 giving 1/1024, 100000 0000 giving 512/1024, etc.

Table 2 Data Acquisition Channels

Logical1 Channel Module # Input

0 FWD HVPS HTR VOLT See Table 1 New Data Acquisition Channels 1 FWD HVPS COLL VOLT See Table 1 New Data Acquisition Channels 2 FWD HVPS CATH VOLT See Table 1 New Data Acquisition Channels 3 -12 VDC Fwd VR 4 -6 VDC Sub Det VR (FWD) 5 LVPS Module #1 (A1A1PS1) +5.1 VDC

6 +12 VDC

7 -12 VDC

8 LVPS #1 Overtemp 9 FWD HVPS COLL CURR See Table 1 New Data Acquisition Channels 10 AFT HVPS HTR VOLT See Table 1 New Data Acquisition Channels 11 LVPS Module #2 (A1A2PS1) +64 VDC

12 +5.2 VDC #2

13 LVPS #2 Overtemp 14 AFT HVPS COLL VOLT See Table 1 New Data Acquisition Channels 15 CB2 OVERLOAD (Pump Acc, LVPS 1 & 2) 16 AFT HVPS CATH VOLT See Table 1 New Data Acquisition Channels 17 AFT HVPS COLL CURR See Table 1 New Data Acquisition Channels 18 Spare 19 Spare 20 Spare 21 Spare 22 Spare

23 BIT LOGIC (PEAK DETECTOR)

24 +15.1 VDC LVPS #2

25 -15.1 VDC LVPS #2

26 +12 Fwd VR 27 +12 Aft VR

28 -20 VDC LVPS #1

29 -12 Aft VR

30 +28 VDC LVPS #1

31 -6 TG VR (AFT)

I/O write to this location starts the conversion B002H

MSB LSB

Word whose LSB is at B002H

I/O write to this location sets Channel # and scale factor B000H

B7 B0

Input: 10 bit scale factor Bits 15-6

Channel # Bits 5-0

Output: I/O read from this location yields converted value.

Bits 7-0 Output Value

Output value is 8 bit offset binary. Values represented in offset binary can be converted to 2’s complement representation by complementing the MSB.

Table 3 Interface Description

Function I/O Type Size Comments VCO Address O Serial 4 bits address 10 VCOs VCO Tune Word O Serial 1 start bit 12 data bits

System Control Unit I/O Register Input: 2X8 bits Output: 1X8 bits

Priority Threshold Control O Register 2X8 bits Subband Select, Data Registers

Noise Subband Multiplex Buffer

O Data RAM 1X16X8 bits Dual port RAM

AGO beamport select O Register 2X8 bits Contains beamport select fwd/aft

AGO subband calibration O Register 2X8 bits AGO subband select data registers

High Voltage Power Supply Status

I/O Parallel 4 bits control output 8 bits input 1 bit strobe input 1 bit ready line output

Noise Beamport Multiplex Buffer

O Data RAM 2X16X8 bits Fwd/Aft beamports select in noise mode

Propeller Beam Multiplex Buffer

O Data RAM 1X8X8 bits Beamport sequence for prop beam.

Single sequence used for both fwd and aft

Paged memory control O Register 1X8 bits B0-B2 only used Technique Generator Interface I/O Serial 4 parallel address lines 8 bits data

Lines are differential pairs.

Receiver Detection Buffer I/O Parallel 1024X8 bits 2 buffers RWR Interface I/O Serial 8 bits RS-422 Subband ON/OFF control O Register 1X8 bits Input Status Receiver/Transmitter

I Parallel 1X8 bits Not latched

Output Receiver/Transmitter O Parallel 1X8 bits Test Port Serial Interface I/O Serial 8 bits RS-232C test interface MLV/ASE Serial Interface I/O Serial 8 bits RS-232C Parallel Input Port I Spare Receiver AOA Beamport Select O Register 2X8 bits Priority Beam Select O Register 2X8 bits Subband Technique Register O Register 8X8 bits PIO Test Register I/O Register 2X8 bits Allocated by tech & subband Data Acquisition Channels I Channels 32 maximum See appendix B

Table 3 Interface Description

Function I/O Type Size Comments PD/CW Status I Register 2X8 bits Dynamic Allocation Repeater/KO Beamport Select I Register 16X8 bits Allocation by subband, fwd, aft beamports

BIT Status Register O Register 2X8 bits 2 output, 1 input register

RWR Transmitter Register O Register 1X8 bits Low Band VCO Address O Address strobe Not used

Low Band VCO Setting & Cal O Serial Not used PD RAM O Data RAM 2X16X8 bits Subband enable, pulse width, & hit count

Table 4 I/O Memory Space Map

I/O Address (Hexadecimal)

Register RAD Paragraph

0000:7000 Receiver Detection Buffer 1.1 8000 Channel a - MLV RS-232C

Channel b – LBC (RLB) Interface 1.43

8200 Channel a - RWR Interface Channel b - TG Data

1.44

8400 TG Serial Receiver Enable 1.45 8600 VCO Control 1.17 9200 Spare 9400 Spare

9600:960E HVPS Controller 1.48 A080:A0AE Spare

A090 Output Status 1 1.2 A092 Output Status 2 1.3 A094 AGO Beamport Select - Fwd. 1.4 A096 AGO Beamport Select - Aft. 1.5 A098 AGO Subband Select 1.6 A09A AGO Calibration Data 1.7 A09C Receiver AOA Beamport Select - Fwd. 1.10 A09E Receiver AOA Beamport Select - Aft. 1.11 A0A0 Priority Beamport Select - Fwd.

A0A2 Priority Beamport Select - Aft.

1.22

A0A4 Priority Threshold Control - Addresses A0A6 Priority Threshold Control - Data

1.16

A0A8 BIT Register 1 (Output) 1.33 A0AA BIT Register 2 (Output) 1.34 A0AC Multiplex Buffer Enable 1.15

Table 4 I/O Memory Space Map

I/O Address

A0AE Receiver Subband ON/OFF Control 1.12 A0B0 Subband Technique Register - MA 1.24 A0B2 Subband Technique Register - MB1 1.25 A0B4 Subband Technique Register - MB2 1.26 A0B6 Subband Technique Register - MB3 1.27 A0B8 Subband Technique Register - MC 1.28 A0BA Subband Technique Register - HA 1.29 A0BC Subband Technique Register - HB 1.30 A0BE Subband Technique Register - HC 1.31 A0C2 Spare A0C4 RWR Xmit Tag Register 1.32 A0C6 Low Band VCO Address Strobe (not used) A0C8 Spare A0CA Spare A0CC SCU Button (Output) 1.21 A0CE Spare A0CO PIO Test Register (Output) 1.36 A0D0 Repeater/KO Beamport Select Fwd. - MA A0D2 Repeater/KO Beamport Select Fwd. - MB1 A0D4 Repeater/KO Beamport Select Fwd. - MB2 A0D6 Repeater/KO Beamport Select Fwd. - MB3 A0D8 Repeater/KO Beamport Select Fwd. - MC A0DA Repeater/KO Beamport Select Fwd. - HA A0DC Repeater/KO Beamport Select Fwd. - HB A0DE Repeater/KO Beamport Select Fwd. - HC A0E2 Repeater/KO Beamport Select Aft. - MB1 A0E4 Repeater/KO Beamport Select Aft. - MB2 A0E6 Repeater/KO Beamport Select Aft. - MB3 A0E8 Repeater/KO Beamport Select Aft. - MC A0EA Repeater/KO Beamport Select Aft. - HA A0EC Repeater/KO Beamport Select Aft. - HB A0EE Repeater/KO Beamport Select Aft. – HC A0EO Repeater/KO Beamport Select Aft. - MA

1.18

A0F0 BIT Status Register 3 (Input) 1.35 A0F2-A0F3 PD/CW Status (LSB)

A0F4 Input Status - Receiver/Transmitter A0F6 PIO Test Register (Input) 1.37 A0F8 SCU System Status (Input) 1.19 A0FA SCU Button Status (Input) 1.20

A0FC-A0FD PD/CW Status (MSB) 1.11 A200:A21E Noise Decoding Buffer 1.13

Table 4 I/O Memory Space Map

I/O Address

A220:A23E Noise Beamports Fwd A240:A25E Noise Beamports Aft

1.14

A260:A27E Propeller Beams Fwd, Aft 1.23 A280:A29E PD Subband Enable 1.40 A2A0:A2BE PD Hitcount, Pulse Width 1.41 B000:BFFF Data Acquisition

1.49

C000:CFFE Instrumentation Interface (deleted)

D000:DFFE Non-Volatile BIT Memory

F600 Paged Memory Control 1.42 F800 TG Interrupt (MPST1-) 1.46 FA00 Master Cycle Strobe (MCYCL-) FC00 Deadman Timer FE00 Boot Disable

2. TECHNIQUES GENERATORS

2.1 FAST TECHNIQUE GENERATOR RN2 MEMORY MAPPED I/O SPACE

RN2 TG4 A3A2A2A14

RN3 A3A2A2A15

RN1 A3A2A2A16 for MB1 A3A2A2A17 for MC A3A2A2A18 for HB A3A2A2A19 for HC

Address Space Allocation 0000-01FF Boot PROM

2000-3FFF RAM

4000 NHW1- MB1 RN1 RAM Data B0-B7 4400 NHW1- MC RN1 RAM Data B0-B7 4800 NHW1- HB RN1 RAM Data B0-B7 4C00 NHW1- HC RN1 RAM Data B0-B7

5000 A3A2A2A16 MB1 RN1 PWA Control register address strobe NH1S+ B0 LOADx- RAM Load enable- B1 RSWKx- PROM output enable+ B2 BST1+ PROM output Amplitude modulation enable- B3 AID1+ RAM output Amplitude modulation enable- B4 U9-12 RAM address cycling control:

0= Chop Phase, 1=KO B5 Not used B6 Not used B7 Not used x = 1 = MB1 x = 2 = MC x = 3 = HB x = 4 = HC

5400 A3A2A2A17 MC RN1 PWA Control register address strobe NH2S+ B0 LOADx- RAM Load enable- B1 RSWKx- PROM output enable+ B2 BST1+ PROM output Amplitude modulation enable- B3 AID1+ RAM output Amplitude modulation enable- B4 U9-12 RAM address cycling control:

0= Chop Phase, 1=KO B5 Not used B6 Not used B7 Not used x = 1 = MB1 x = 2 = MC x = 3 = HB x = 4 = HC

5800 A3A2A2A18 HA RN1 PWA Control register address strobe NH3S+ B0 LOADx- RAM Load enable- B1 RSWKx- PROM output enable+ B2 BST1+ PROM output Amplitude modulation enable- B3 AID1+ RAM output Amplitude modulation enable- B4 U9-12 RAM address cycling control:

0= Chop Phase, 1=KO B5 Not used B6 Not used B7 Not used x = 1 = MB1 x = 2 = MC x = 3 = HB x = 4 = HC

5C00 A3A2A2A19 HC RN1 PWA Control register address strobe NH4S+ B0 LOADx- RAM Load enable- B1 RSWKx- PROM output enable+ B2 BST1+ PROM output Amplitude modulation enable- B3 AID1+ RAM output Amplitude modulation enable- B4 U9-12 RAM address cycling control:

0= Chop Phase, 1=KO B5 Not used B6 Not used B7 Not used x = 1 = MB1 x = 2 = MC x = 3 = HB x = 4 = HC

6000 LAT1- MB1 RN1 RAM Address Latch A3A2A2A16-U5 data B0-B5 RAM Address data B6 R1/R2 Technique select U5-16 B7 R2 Amplitude Modulation enable U5-19

6400 LAT2- MC RN1 RAM Address Latch A3A2A2A17-U5 data B0-B5 RAM Address data B6 R1/R2 Technique select U5-16 B7 R2 Amplitude Modulation enable U5-19

6800 LAT3- HA RN1 RAM Address Latch A3A2A2A18-U5 data B0-B5 RAM Address data B6 R1/R2 Technique select U5-16 B7 R2 Amplitude Modulation enable U5-19

6C00 LAT4- HC RN1 RAM Address Latch A3A2A2A19-U5 data B0-B5 RAM Address data B6 R1/R2 Technique select U5-16 B7 R2 Amplitude Modulation enable U5-19

7000 WALK1- MB1 RN1 PROM Address latch A3A2A2A16-U B0-B6 PROM Address B7 Dual pulse enable

7400 WALK2- MC RN1 PROM Address latch A3A2A2A17-U B0-B6 PROM Address B7 Dual pulse enable

7800 WALK3- HA RN1 PROM Address latch A3A2A2A18-U B0-B6 PROM Address B7 Dual pulse enable

7C00 WALK4- HC RN1 PROM Address latch A3A2A2A19-U B0-B6 PROM Address B7 Dual pulse enable

800x TIME3 – A3A2A2AA15-U12 Timer 3 load data 8000 HC AM timer load data HC PRI 8001 HC AM timer load data HC PW 8002 Unused 8003 Control Reg. 6

A00x TIME2 – A3A2A2AA15-U15 Timer 2 load data A000 MC AM timer load data MC PW A001 HB AM timer load data HB PRI A002 HB AM timer load data HB PW A003 Control Reg. 6

C00x TIME1 – A3A2A2AA15-U20 Timer 1 load data C000 MC AM timer load data MC PRI C001 MB1 AM timer load data MB1 PW C002 MB1 AM timer load data MB1 PRI C003 Control Reg. 6

2.2 FAST TECHNIQUE GENERATOR RN2 PORT ASSIGNMENTS

Port 0 Address A8-A15 Port 1 Address/Data AD0-AD7

Port 2 KO technique control

B0 RG1- MB1 KO Enable- (output) B1 RG2- MC KO Enable- (output) B2 RG3- HB KO Enable- (output) B3 RG4- HC KO Enable- (output) B4 MB1 Minimum delay enable- (output) B5 MC Minimum delay enable- (output) B6 MB Minimum delay enable- (output) B7 HC Minimum delay enable- (output)

Port 3 Serial communications interface

2.3 FAST TECHNIQUE GENERATOR V1 MEMORY MAPPED I/0 SPACE

TG5 A3A2A2A13

TG6 A3A2A2A11

Memory Space Allocation 0000-01FF Boot PROM

2000-3FFF RAM

4000 xLF00-xLF07 Low frequency VCO tune data LSB (output) 6000 xLF08-xLF15 Low frequency VCO tune data MSB (output) x = 1 =TG6, x = 2 = TG5 8000 xFR0-xFR07 High frequency VCO tune data LSB (output) 8080 xFR08-xFR15 High frequency VCO tune data MSB (output) x = 1 =TG6, x = 2 = TG5

C000 U1/U2 VCO frequency measurement data (input) (400Hz/bit)

FE00-FFFF BOOT PROM same as 0000-01FF

2.4 FAST TECHNIQUE GENERATOR V1 PORT ASSIGNMENTS

Port 2 V2 PWA frequency generator control

B0 xDIRE+ UP-/DOWN+ select (output) B1 B00x+ Amp modulation disable request to non-std interface (output) B2 xFRMS+ Low-/High+ frequency VCO select (output) B3 U15P34 VCO frequency measure enable+ (output) B4 xFR0E- VCO enable+ (output) B5 Not used B6 Not used B7 Notused x = 1 = TG6, x = 2 = TG5

Port 3 Serial communications interface.

B3 TuneI- V2 PWA VCO frequency measure complete interrupt (input)

2.5 NON-STANDARD INTERFACE MUX MEMORY MAPPED I/O SPACE

TG7 A3A2A2A7

Memory space allocation

0000-01FF BOOT PROM

2000-3FFF RAM

4000 A3A2A2AA9, TG Fault Logic PWA BIT MUX data. (Input) If address A000 bit B6 is programmed to a TTL 0 B0 MAFAL- MA Noise fault B1 MB2FL- MB2 Noise fault B2 HBFAL- HB Noise fault B3 not used (ko deadman timer is or’ed in from 8000 by TG7 s/w) B4 FVB1- TG6 (A10-A11) V technique generator fault B5 RNFAULT1- MB1 RN technique fault B6 RNFAULT3- HB RN technique fault B7 S1-1 MA Quad modulator technique fault ECP98-01

If address A000 Bit B6 is programmed to a TTL 1 B0 MB1FL- MB1 Noise fault B1 MCFAL- MC Noise fault B2 HCFAL- HC Noise fault B3 U1FAULT- A8 technique discrete generator fault B4 FVB2- TG5 (A12-A13) V technique generator fault B5 RNFAULT2- MC RN technique fault B6 RNFAULT4- HC RN technique fault B7 S1-2 HC Quad modulator technique fault

4000 Subband V technique enables (output)

B0 MB2EN+ MB2 V technique enable B1 MB3EN+ MB3 V technique enable B2 MCEN+ MC V technique enable B3 HAEN+ HA V technique enable B4 HBEN+ HB V technique enable B5 HCEN+ HC V technique enable B6 Not used B7 Not used

6000 Subband V technique generator selects (output)

B0 MB2SE+ MB2 generator select 0=TG6/1=TG5 B1 MB3SE+ MB3 generator select B2 MCSE+ MC generator select B3 HASE+ HA generator select B4 HBSE+ HB generator select B5 HCSE+ HC generator select B6 Not used B7 Not used

8000 FEDVLS- A3A2A2A8 Set-on controller Bit MUX data. (Input) If address A000 bit B5 is programmed to a TTL 1 B0 U7B-8 KO deadman timer fault B1 Not used B2 BITE0 Mod Control A MUXed fast switch BIT commands B3 BITE1 Mod Control A MUXed fast switch BIT commands B4 U13 VCO tune error data bit A0

B5 U13 VCO tune error data bit A1 B6 U13 VCO tune error data bit A2 B7 U13 VCO tune error data bit A3

If address A000 bit B5 is programmed to a TTL 0 B0 U10 VCO tune error data bit B04 B1 U10 VCO tune error data bit B05 B2 U10 VCO tune error data bit B06 B3 U10 VCO tune error data bit B06 B4 U11 VCO tune error data bit B07 B5 U11 VCO tune error data bit B08 B6 U11 VCO tune error data bit B09 B7 U11 VCO tune error data bit B10

C00x DEDSI- A3A2A2A6 noise technique control C000 CONTAA U14-15 MA foreground VCO fill noise amplitude control (output) C001 CONTBA U14-14 MA background VCO fill noise amplitude control (output) C002 CONTCA U14-13 MB1 foreground VCO fill noise amplitude control (output) C003 CONTDA U14-12 MB1 background VCO fill noise amplitude control (output) C004 CONTEA U14-11 MB2 foreground VCO fill noise amplitude control (output) C005 CONT64 U14-10 MC foreground VCO fill noise amplitude control (output) C006 CONTFA U14-09 MC background VCO fill noise amplitude control (output) C007 CONT U14-08 HB foreground VCO fill noise amplitude control (output) C008 U15-15 HC foreground VCO fill noise amplitude control (output) C009 CONT2A U15-14 VCO noise BIT enables (output) B0 U11-02 MA foreground VCO noise BIT enable- B1 U11-05 MA background VCO noise BIT enable- B2 U11-06 MB1 foreground VCO noise BIT enable- B3 U11-09 MB1 background VCO noise BIT enable- B4 U11-12 MB2foreground VCO noise BIT enable- B5 U11-15 MC foreground VCO noise BIT enable- B6 U11-16 MC background VCO noise BIT enable- B7 U11-19 HB foreground VCO noise BIT enable-

C00A U15-13 Lookthrough/bandwidth select (output)

B0 U10-02 MC foreground VCO noise BIT enable- B1 U10-05 MA foreground VCO narrow/wideband fill noise select- B2 U10-06 MB! foreground VCO narrow/wideband fill noise select- B3 U10-09 MC foreground VCO narrow/wideband fill noise select-

B4 LALTS+ LA Subband Lookthrough enable- B5 LBLTS+ LB Subband Lookthrough enable- B6 LARWR+ LA Subband RWR Lookthrough enable- B7 LBRWR+ LB Subband RWR Lookthrough enable-

C00B C00C C00D MCSEL- MC VCO combiner attenuation data (output) C00E MB1SEL- MB1 VCO combiner attenuation data (output) C00F MASEL- MA VCO combiner attenuation data (output)

2.6 NON-STANDARD INTERFACE MUX PORT ASSIGNMENTS

Port 2 V Technique AM modulation control B0 B001+ TG5 AM disable request (input) B1 B002+ TG6 AM disable request (input) B2 AM disable request to MB2 standard waveform PWA (output) B3 AM disable request to MB3 standard waveform PWA (output) B4 AM disable request to MC standard waveform PWA (output) B5 AM disable request to HA standard waveform PWA (output) B6 AM disable request to HB standard waveform PWA (output) B7 AM disable request to HC standard waveform PWA (output)

2.7 STANDARD WAVEFORM GENERATOR MEMORY MAPPED I/O SPACE

TG SB REF DES

8 MA A3A2A2A21

9 MB1 A3A2A2A22

10 MB2 A3A2A2A24

11 MB3 A3A2A2A25

12 MC A3A2A2A26

13 HA A3A2A2A27

14 HB A3A2A2A28

15 HC A3A2A2A29

Memory space allocation

0000-01FF BOOT PROM

2000-5FFF RAM

6800 U7 VCO/Quad Mod sweep tune DAC load data (output) B0 B1 B2 B3 B4 B5 B6 B7 7000 Quadrature Generator PWA U13 VCO frequency measure data (input)

8000 Parameter latch 1 data (output) B0 VCOx1 Quad Mod low freq VCO enable (MA/HC)/A8 PW select B0 MB2 B1 VCOx2 Quad Mod low freq VCO enable (MA/HC)/A8 PW select B1 MB2 B2 VCOx3 Quad Mod low freq VCO enable (MA/HC)/A8 PW select B2 MB2 B3 VCOx4 Quad Mod VCO range select (MA/HC)/A8 PW select B3 MB2 B4 xESWC Quad Mod track/hold (MA/HC)/A8 PW select B4 MB2 B5 FRxST Quad Mod frequency counter clear command (MA/HC)

B6 x1SPD Quad Mod frequency measure enable gate (MA/HC) B7 Not used x=1/3/8 for MA/MB2/HC

A000 Parameter Latch data 2 (output) B0 SxREW RF fast switch ON/OFF control B1 xxKS+ Repeater/KO fast switch RF routing select B2 xxRP+ Repeater AM control B3 xWSE1 Quad Mod UP/DOWN mod select (MA/HC)/A8 duty cycle (MB2) B4 xWSE2 Quad Mod UP/DOWN mod select (MA/HC)/A8 duty cycle (MB2) B5 R/N- Route atten DAC output to repeater (xxRA+) or noise (xxNA+) B6 xDA1 U18 VCO sweep tune DAC MSB B7 PRESCEN- Sweep tune DAC counter clock prescaler enable

C000 U7 Repeater/Noise Attenuator DAC data (output)

2.8 STANDARD WAVEFORM GENERATOR PORT ASSIGNMENTS

Port 2 General I/O B0 U18 Sweep Tune DAC BIT test point (input) B1 U7 Attenuation DAC BIT test point (input) B2 xxBO+ Amplitude Mod disable request (input) B3 AGOxS+ AGO RF fast switch path enable (output) B4 BIT0x+ Z8 BIT status to TG fault logic (output) B5 RWRBRx+ RWR blanking enable (output) B6 DMBSx+ Dual Mod bias select (MB2) (output) B7 Not used x= 1/2/3/4/5/6/7/8 for…