RFQ_DJF-16-1800-PR-0006398_PCIe_Ethernet_Tap.pdf

RFQ 0006398

RFQ 0006389

This is a combined synopsis/solicitation for commercial items prepared in accordance with the format in

FAR Subpart 12.6, supplemented with additional information included in this notice in using FAR Part

13.5. This solicitation is a small business set aside. The solicitation number is RFQ0006398 and is issued as a Request for Quote (RFQ). This solicitation document and incorporated provisions and clauses are those in effect through Federal Acquisition Circular FAC 2005-87. The associated North American

Industrial Classification System (NAICS) code for this procurement is 541512 .

The Federal Bureau of Investigation requests open market pricing for a PCIe Ethernet Tap. If these descriptive(s) are not included in the submitted quote, the quote could be considered “unresponsive.”

Attachment:

1. Specifications

2. Block diagram and notes in the accompanying file “2016-03-01 PCIe Tap - Block

Diagram.pdf

Shipping: All deliveries under this order shall be FOB destination. All items procured under this order will be delivered to Quantico, Virginia.

Period of Performance:

The period of performance shall be proposed by each offeror.

The offeror shall provide a deliver schedule for each CLIN as follows:

CLIN 0001 ___________________

CLIN 0002 ___________________

CLIN# Description Qty

Design of PCIe Ethernet Tap 1

0002 Reproduction of designed PCIe Ethernet Tap 100

0003 Shipping and Handling 1

U.S. Department of Justice

Federal Bureau of Investigation

CLIN 0003 ___________________

Delivery Requirement

All items will be shipped to:

Federal Bureau of Investigation

Engineering Research Facility

Bldg 27958-A

Quantico, VA 22135

Invoicing:

Progress payments will be allowed and all invoices will only be paid at the end of each deliverable and upon acceptance.

INVOICE SUBMISSION PROCESS:

The invoice should be attached to an email, and sent to the following address:

central_invoices@ic.fbi.gov

It is imperative that the invoice contains current and accurate contract information

(contract/order number), otherwise risks being rejected.

Upon receipt of the invoice, a confirmation email will be sent back to the sending email address. At this point the invoice is considered received, and will begin processing through the FBI’s internal payment systems.

Please note, invoices received before 5pm EST (Monday-Friday) will be considered

“received” that business day. Any invoice received after 5pm EST will be considered

“received” and will be entered into the invoice system on the following business day.

Small Business Accelerated Payment

The Contractor must indicate his business size on each invoice to assist the payment office in determining eligibility for accelerated payment in accordance with OMB Memo

M-11-32, “Accelerating Payments to Small Businesses for Goods and Services,” dated

10/14/2011. The Prompt Payment Act still applies to this action. However, the agency will make best efforts to pay proper invoices within 15 days.

**Question Submission: Interested offerors must submit any questions concerning the solicitation at the earliest time possible to enable the Buyer to respond. Questions may be submitted to the attention of Dorothy Romo at Dorothy.Romo@ic.fbi.gov, no later than

Wednesday, March 30, 2016 at 9:00 AM (Eastern).

1. New Equipment only will be accepted for this procurement.

2. Quote must be valid for 90 days from closing of posting.

3. Delivery must be identified within the terms and conditions of the quote

4. The government terms and conditions remain enforceable over the contractor terms and conditions.

mailto:Dorothy.Romo@ic.fbi.gov

The selected offeror must comply with the following commercial item terms and conditions, which are incorporated herein by reference: FAR 52.212-1, Instruction to Offerors-Commercial

Items, applies to this acquisition; FAR 52.212-3, Offeror Representations and Certifications-

Commercial Items-the selected offeror must submit a completed copy of the listed representations and certifications; FAR 52-212-4, Contract Terms and Conditions-Commercial

Items; FAR 52-212-5, Contract Terms and Conditions Required to Implement Statutes or

Executive Orders-Commercial Items, paragraph (a) and the following clauses in paragraph (b):

52.222-21, 52.222-26, 52.222-35, 52.222-36, 52.222-37, 52.225-13, 52.232-34. The full text of the referenced FAR clauses may be accessed electronically at https://www.acquisition.gov/far/.

Quotes

Quotes must be received by Wednesday, April 6, 2016 at 9:00 AM (Eastern). Quotation/offer and any accompanying information may be e-mailed to Dorothy.Romo@ic.fbi.gov. Offers must be valid for 90 calendar days after submission.

In order to be considered technically acceptable you must provided a technical proposal that demonstrates your ability to provide a PCIe Ethernet Tap that meets or exceeds the description above. You must also provide relevant past performance indicating that you have successfully designed/built PCIe Ethernet Tap.

Please include in your quote: pricing and product description for each line item listed above.

Quote may be sent via your company’s standard quotation form but must include the following information: Tax ID #, DUNS #, Point of Contact with Email and telephone information.

Evaluation Factors:

Award will be made to the lowest price/technically acceptable offeror.

Corporate Representation Regarding Felony Conviction Under Any Federal Law or

Unpaid Delinquent Tax Liability – Solicitation (DEVIATION 2015-02) (March 2015)

(a) None of the funds made available by the Department’s current Appropriations Act may be used to enter into a contract, memorandum of understanding, or cooperative agreement with a corporation –

(1) convicted of a felony criminal violation under any Federal law within the preceding 24 months, where the awarding agency is aware of the conviction, unless an agency has considered suspension or debarment of the corporation and made a determination that this further action is not necessary to protect the interests of the Government, or

(2) that has any unpaid Federal tax liability that has been assessed, for which all judicial and administrative remedies have been exhausted or have lapsed, and that is not being paid in a timely manner pursuant to an agreement with the authority responsible for collecting the tax liability, where the awarding agency is aware of the unpaid tax liability, unless an agency has considered suspension or debarment of the corporation and made a determination that this further action is not necessary to protect the interests of the Government.

(b) By submitting a response to this solicitation, the offeror represents that, as of the date of this offer –

(1) the offeror is not a corporation convicted of a felony criminal violation under any Federal or State law within the preceding 24 months; and, mailto:%20Dorothy.Romo@ic.fbi.gov

(2) the offeror is not a corporation that has any unpaid Federal or State tax liability that has been assessed, for which all judicial and administrative remedies have been exhausted or have lapsed, and that is not being paid in a timely manner pursuant to an agreement with the authority responsible for collecting the tax liability.

(End of Provision)

Contractor Internal Confidentiality Agreements or Statements Prohibiting or Restricting

Reporting of Waste, Fraud, and Abuse- Solicitation

(DEVIATION 2015-02) (March 2015) None of the funds appropriated to the Department under its current Appropriations Act may be used to enter into a contract, grant, or cooperative agreement with an entity that requires employees or contractors of such entity seeking to report fraud, waste, and abuse to sign internal confidentiality agreements or statements prohibiting or otherwise restricting such employees or contractors from lawfully reporting such waste, fraud, or abuse to a designated investigative or law enforcement representative of a Federal department or agency authorized to receive such information. By submitting a response to this solicitation, the contractor certifies that it does not require employees or contractors of the contractor seeking to report fraud, waste, and abuse to sign internal confidentiality agreements or statements prohibiting or otherwise restricting such employees or contractors from lawfully reporting waste, fraud, and abuse to a designated investigative or law enforcement representative of a Federal department or agency authorized to receive such information.

(End of Provision)

SAM Requirement

Note: Ensure your firm is registered in System for Award Management (SAM) - All vendors must be registered in SAM, effective July 29, 2012, to receive government contracts.

The FBI is utilizing a new financial system that has a direct interface with the SAM. If any current FBI vendor data conflicts with SAM Data, the information contained in SAM may override our current information. Please ensure that your company’s SAM information is updated and accurate. This includes: TIN, EFT, DUNs, addresses and contact information. The

EFT banking information on file in SAM will be what the FBI uses to process payment to your organization.

RJ45

512MB (min)

1333 DDR3 (min)

SDRAM

2GB (min)

1333 DDR3 (min)

SDRAM

PCIe Interface, Gen2 x4

FPGA Config

Flash Memory

RS232 Level

Translate

(3.3V)

6-pin 0.1"

Header

N o n -latch in g relay s

Q u ad

/1

/1

P

H Y

Micro

USB Connector

Xilinx Zynq

XC7030-3 E/I

1GHz Dual-core Cortex-A9

125k Logic Cells (Kintex-7)

265 36kb BRAM

PL

RGMII

HSPTap

1 March 2016

PS MIO UART

PS MIO USB2

- Low-profile, half-length PCIe board (Gen2 x4 electrical & mechanical interface)

- No supplemental power – powered by PCIe interface only

- Integrated Ethernet 10/100/1000Base-T tap, user-selectable as one tapped bidirectional line or two SPAN inputs to PHY/FPGA

- FPGA & Cortex-A9 Config flash memory reprogrammable via host application over PCIe interface (Windows Svr 2012 R2-compatible)

PS MIO

RGMII

PS

PL

RJ45

RJ45

Digilent

USB-to-JTAG

Interface

Micro

USB Connector

PS MIO GPIO

Micro

USB Connector*

PS MIO

MDIO

PL USB2

* If mechanically possible, the PL USB connector should provide an external interface through the mounting plate; if not possible, the connector should be mounted on the opposite side of the board to provide an internal interface

50?-pin 0.1"

Debug Header

DIP Switch

Header blk

LEDs

PL

RGMII

PCIe Ethernet Tap Specifications:

Note: This document is supplemented with the block diagram and notes in the accompanying file “2016-03-01 PCIe Tap - Block Diagram.pdf”

1. PCIe form-factor, half-length (max of 6 5/8 inches), half-height (max of 2 1/4 inches), and occupies a single slot (max thickness of 11/16 inches)

2. Both half-height and full-height mounting plates shall be provided for all delivered boards

3. External interfaces shall be:

a. Three RJ45 connectors suitable for 10/100/1000 Base-T Ethernet, accessed through the mounting plate

b. PCIe Gen2 x4 interface to the host for communication and power to the board

c. If possible to fit on the mounting plate with the RJ45 connectors specified in 3a above, a micro USB connector should be accessible through the mounting plate to provide a USB

2.0 interface to the Programmable Logic (PL)

4. Internal interfaces shall be:

a. 6-pin 0.1" header providing RS232 connectivity to the FPGA, compatible with the FTDI TTL-232R-3.3V USB-to-RS232 interface cable (see attached mechanical spec)

b. Micro USB connector on the back of the board (opposite side of the mounting plate) to provide a USB 2.0 interface to the Processing Subsystem (PS)

c. Micro USB connector on the back of the board to provide JTAG connectivity to the FPGA and configuration memory through the Digilent USB-to-JTAG converter

d. A 20-pin connector compatible with the ARM DSTREAM debug adapter to provide connectivity to the PS PJTAG interface

e. If the micro USB connector from specification 3c cannot be installed through the mounting plate, then this connector shall be made available on the back side of the board, and shall provide a USB 2.0 interface to the PL

f. 50-pin 0.1” header connected to unused PS GPIO pins and to unused I/O pins to the PL for debug – note: this connector may be split into multiple, smaller headers to facilitate placement on the board and available I/O in the FPGA, and should include at least two pins per block tied to digital ground.

5. A Xilinx Zynq 7030 (E or I temperature grade) shall be used to provide a 1GHz dual-core Cortex-A9 Processing Subsystem (PS) as well as Programmable Logic (PL) capabilities

6. 1333 MHz (or faster) DDR3 SDRAM selection shall be compatible with the native PS interface and standard memory configuration tool in the Xilinx Vivado tool; no 3rd party IP core and integration shall be allowed

7. The PCIe interface within the PL must be configured and functional within the minimum PCIe spec of 100 msec after a power-on cycle. This shall be done with a "tandem" boot mode as described by Xilinx for the Zynq part, with the remainder of the FPGA configuration continuation out of flash memory.

8. The non-latching relays connecting the two Ethernet RJ45 ports and the quad PHY will implement a physical-layer “tap” capability under control of the PS. When not energized, the relays will connect the two RJ45 ports together, implementing a physical “bypass” mode of the circuitry on the board; when the relay is energized, each RJ45 will be connected to their respective port on the PHY, where the Ethernet connection will be electrically terminated.

9. Sufficient thermal analysis and component heat-sinks shall be provided (if necessary).

Assumed operating conditions include the following:

a. All three Ethernet interfaces connected and transferring data at 1Gbps rate in both directions

b. 75% of all FPGA logic and block RAM utilized

c. 50% of all FPGA internal flip-flops toggling at 125MHz rate

d. Both PS cores executing at 1GHz rate out of PS SDRAM

e. PL streaming (reading and writing) data to the PL SDRAM at a ~10% utilization rate

(3Gbps in each direction)

f. Continuous bidirectional data transfers across the PCIe bus at a ~20% utilization rate

(3Gbps in each direction – board writing to and reading directly from host memory)

10. Power for the board shall be provided only by the PCIe interface

11. A Windows 10/7/Server 2012 application shall be provided that programs the FPGA configuration flash memory over the PCIe bus (includes any necessary FPGA interface & software that must be integrated into the final product to support this)

12. DIP switch(es), LEDs, and 0.1” through-hole header blocks shall be provided on the board as follows:

a. FPGA configuration mode will be selectable through three header pin pairs

b. 2-bit input to PS GPIO using header pin pairs

c. 2-bit input to PL I/O using header pin pairs

d. 4-bit DIP switch input to PS GPIO

e. 4-bit DIP switch input to PL I/O

f. 4-bit LED driven by PS GPIO

g. 8-bit LED driven by PL I/O

h. LEDs to indicate FPGA configuration status (DONE), and power supply status

13. Both the FPGA’s dedicated and the PS JTAG interfaces shall be available, and switch-selectable into cascaded or independent mode. In independent mode, the PS PJTAG port shall be accessible via a 20-pin connector compatible with the ARM DSTREAM debug adapter, and the FPGA & configuration memory JTAG interface shall be accessible via the Digilent USB-to-JTAG interface. In cascaded mode, the JTAG path connectivity shall be user-switchable to either of the Digilent or 20-pin connector.

14. One or more FPGA configurations shall be delivered that demonstrate successful interface and component operation. Minimal supporting user interfaces are acceptable, such as using the Xilinx Vivado Logic Analyzer tool, RS232/console streaming, etc. The testing shall include as a minimum:

a. Received Ethernet frame counter on each of the three copper Ethernet interfaces, including accompanying FCS error counts

b. Memory test of each of the two banks of SDRAM (one by the PS, and one through the

PL)

c. Data transfer test across the PCIe bus, to demonstrate bandwidth and data integrity

d. Operation of all interfaces, including but not limited to, the Ethernet relays, USB interfaces, RS232 and JTAG connectivity.

Deliverables:

CLIN 0001:

• Final electrical design – schematics (searchable PDF-format), bill of materials (BOM)

• Final PCB board design – stackup, Gerbers, etc

• 5 Prototype boards, with a following 2-week period for customer acceptance of the implementation

• Windows 10/7/Server 2012 R2-compatible application to program flash configuration memory from the host, including all source code & project assembly documents needed to implement

CLIN 0002:

• 100 boards (post prototype-acceptance)

DJF-16-1800-PR-0006398 PCIe Ethernet Tap Specifications REV 1