Q&A.pdf

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SIR/RFO: MAU Single Board Computer
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DTFAAC-17-R-00171
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SIR Section Title Vendor Question

Date Question

Submitted Government Response

Section J Attachment 3: Compliance Matrix

Please provide clarification on what values A[31:24] need to be (either 0x00, 0xFF, or 0xZZ ‐ high impedance) transacation.

14‐Jul‐17 During an A24 address cycle, A[31:24] must be 0x00.

DTFAAC‐17‐R‐00171

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