Downstate Semiconductor Chip Design Center
Open State & local contract opportunity Posted
- Solicitation number
- 2138328
- State
- New York
- Responses due
Opportunity facts
- Point of contact
Updated .
About this opportunity
Empire State Development (ESD) is requesting applications to design, construct, develop, and operate a Semiconductor Chip Design Center in downstate New York, with the Phase 1 Concept Paper due October 26, 2026. Eligible applicants are restricted to 501(c)(3) nonprofit organizations, academic or research institutions, or consortia of two or more eligible entities with one designated lead applicant as fiscal agent. Specific MWBE and SDVOB participation goals will be established on a grant-by-grant basis, with agency-wide targets of 30 percent MWBE participation (15% MBE, 15% WBE) and 6 percent SDVOB participation.
Downstate is defined as Putnam, Dutchess, Orange, Rockland, Westchester, Nassau, and Suffolk counties, plus New York City's five boroughs. The Center must provide shared access to industry-standard electronic design automation tools, computing resources, and secure design environments; support early-stage chip design innovation including architecture development and design verification; incubate and accelerate chip design and semiconductor startups; and deliver workforce development and training programs for New York residents pursuing high-skill chip design roles. The Center may involve new construction, expansion, or modification of an existing structure and leverage State support alongside industry, academic, and philanthropic partnerships.
Grant funding of up to $25 million covers eligible capital costs including new construction, renovation, leasehold improvements, machinery and equipment, demolition and environmental remediation, furniture and fixtures, and soft costs up to 25 percent of eligible capital expenditures. No cost-match requirement applies. Ineligible expenses include developer fees, in-kind costs, and overhead and indirect costs. Recipients must submit annual performance reports for up to five years following project completion, with recapture and repayment provisions if material program requirements are not satisfied.
The RFA follows a three-phase process: Phase 1 (Concept Paper) is due October 26, 2026 by 2:00 PM EST; Phase 2 (Interactive Review) is scheduled November 9–20, 2026; Phase 3 (Full Proposals) is due January 11, 2027. Anticipated selection is February 2027, with contract start July 2027. An informational webinar is scheduled September 17, 2026 at 12:00 PM (RSVP by September 16). Questions are due September 22, 2026, with answers posted by October 2. Applications are submitted via email to DownstateSemiconductorChipDesign2026@esd.ny.gov.
Opportunity text
Under this RFA, ESD anticipates selecting one qualified organization to lead the design, construction, development and operation a world-class Semiconductor Chip Design Center located in downstate New York. The creation of the Center may involve multiple partnersand could be a new building and/or the expansion or modification of an existing structure. "Downstate", in the context of this RFA, shall refer to the counties of Putnam, Dutchess, Orange, Rockland, Westchester, Nassau, Suffolk, and the five boroughs of New York City. Applicants are expected to deliver against the following program objectives:Center Establishment and Operations• Build and manage a physical semiconductor chip design center in downstateNew York.• Establish a sustainable operating model that leverages State support alongsideindustry, academic, and philanthropic partnerships. Access to Advanced Chip Design Tools and Infrastructure• Provide shared access to industry-standard electronic design automation (EDA)tools, computing resources, and secure design environments.• Reduce barriers to market entry for early-stage firms, academic teams, andemerging designers who lack the resources to independently access advanceddesign platforms.Chip Design Research, Prototyping, and Validation• Support innovation in early-stage chip design, including architecturedevelopment, design verification, and pre-manufacturing validation.• Facilitate pathways to fabrication by connecting design efforts with manufacturingand prototyping resources.Startup Incubation and Commercialization Support• Incubate and/or accelerate chip design and related semiconductor startups byproviding access to design tools, guidance on intellectual property strategy,information on commercialization pathways, and connections to investors andstrategic partners.Workforce Development and Talent Pipeline• Deliver training programs that prepare New York residents for high-skill chipdesign roles, including upskilling and/or reskilling opportunities.Performance Measurement and Reporting• Establish metrics to track outcomes, including number of startups supported,designs advanced, and partnerships formed.• Provide regular reporting to New York State on progress, challenges, and impact. Business enterprises awarded an identical or substantially similar procurement contract within the past five years: None Service-Disabled Veteran-Owned Business (SDVOB) SDVOB Goal: 6.00% Minority / Women Business Enterprise contracting goals (MWBE) MBE Goal: 15.00% WBE Goal: 15.00%
Files
| File | Type | Posted |
|---|---|---|
| Downstate Semiconductor Chip Design Center_2026 RFA .pdf |
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