A02_-_PWS_(Sayma_Software).docx

Performance Work Statement (PWS) Software Support for Sayma v2.0 PCB

C.1.0 BACKGROUND

The Quantum Science Branch (FCDD-RLS-EQ) in the Sensors and Electron Devices Directorate (SEDD) at the Army Research Laboratory (ARL) performs a variety of quantum computing and quantum networking experiments using trapped atomic ion quantum bits (qubits). The complexity of these experiments necessitates substantial automation.

The Advanced Real-Time Infrastructure for Quantum physics (ARTIQ) is an open source operating system (OS) for managing complex automated experiments. Sinara is an ecosystem of printed circuit boards (PCBs) and open standards designed explicitly for the ARTIQ OS that provides functionality including waveform generation, waveform digitization and logical input/output. Sinara specifies standards for clock distribution, data distribution, device interconnect and synchronization.

A discussion of the predecessor control system and details on its implementation is provided in the following dissertation:

“High Fidelity Quantum Information Processing with Trapped Ions” by Christopher E. Langer, University of Colorado at Boulder, 2005, pp. 106-132.

http://www.nist.gov/pml/div688/grp10/upload/langer_phdthesis.pdf

Technical terminology used herein is explained in the ARTIQ manual and public codebase. And in the Sinara public codebase.

https://github.com/m-labs/artiq https://m-labs.hk/ https://sinara-hw.github.io/

Hardware and software solutions available in the marketplace do not provide the performance necessary for next-generation quantum information experiments. In particular, there is a need for low-cost, many-channel, phase synchronous waveform generators compatible with ARTIQ and other elements of the Sinara hardware ecosystem. To meet this need ARL supports the development of the Sayma PCB and its integration with the ARTIQ OS. This development will enable quantum computing and networking research conducted by the Quantum Science Branch using trapped atomic ion qubits.

Core components of the Sayma hardware functionality are implemented in Field Programmable Gate Arrays (FPGAs) which require configuration instructions known as “gateware.” This PWS focuses on the development of software, firmware and gateware needed to enable functionality of revision 2.0 of the Sayma PCB.

The Sayma v2.0 PCB consists of several hardware components: Sayma AMC PCB, Sayma RTM PCB, BaseMod PCB and Metlino PCB. The schematics, layout and design-related discussions for these hardware components are located at the following github repositories.

https://github.com/sinara-hw/Sayma_AMC https://github.com/sinara-hw/Sayma_RTM https://github.com/sinara-hw/BaseMod https://github.com/sinara-hw/metlino A prior contract awarded in 2017 (W911QX17P0075) concerned the predecessor hardware, Sayma v1.0. Support for Sayma v1.0 is provided in ARTIQ release 4.0.

https://github.com/sinara-hw/sinara/tree/master/ARTIQ_EE https://github.com/m-labs/artiq/blob/4.0 https://github.com/m-labs/artiq/blob/4.0/artiq/gateware/targets/sayma_amc.py https://github.com/m-labs/artiq/blob/4.0/artiq/gateware/targets/sayma_rtm.py

C.2.0 OBJECTIVE

The Government requires a software development Contractor with strong familiarity with ARTIQ, Sinara hardware, Sayma Smart Arbitrary Waveform Generator (Sayma SAWG) and the Sayma PCB v1.0 who can provide support for the forthcoming Sayma PCB v2.0. This PWS defines variety of tasks that emphasize design of and support for a new revision of the Sayma hardware. The tasks include porting prior work on the v1.0 hardware to the v2.0 hardware and development of core capabilities including synchronization.

C.3.0 REQUIREMENTS

The Contractor shall design and test software, firmware and gateware in support of operation of the Sayma v2.0 PCBs with the ARTIQ OS. The Contractor shall provide suitable test benches and unit tests, in accordance with Section C.3.3 “Technical Requirement Specifications” below. The supplied solution will be tested by ARL upon receipt to ensure performance in accordance with Section 3.2 “Deliverables” below.

The necessary software, firmware and gateware form a complex package that require the Contractor to have detailed understanding of the ARTIQ operating system and the Sinara hardware ecosystem. See also Section C.3.1 “Contractor Qualifications".

C.3.0.1 DAC-FPGA Synchronization Deterministic phase alignment is required between digital to analog converters (DACs) on separate Sayma PCBs between power cycles. This design criterion and should be considered at all stages of design. This requirement implies a) SYSREF clock is aligned with the Real-Time Input-Output (RTIO) clock b) DAC clocks are synchronized to local SYSREF clock edges.

· Test conditions

· SAWG output on all channels on two Sayma boards

· Sayma-local ARTIQ TTL PHY output at 62.5 MHz

· using existing RTIO infrastructure and TTL PHY

· laboratory temperature stability +/- 0.5 C

· cycle crate power 100 times

· Specification

· ST1: SAWG-SAWG phase alignment error across all power cycles: < 1/f_dac_clk

· ST2: SAWG to TTL alignment error across all power cycles: < 0.5 nanosecond C.3.0.2 DAC Phase Stability Phase stability between DACs on separate Sayma PCBs is an important design criterion and should be considered at all stages of the design. This assumes that DAC-FPGA synchronization.

· Test conditions

· SAWG output on all channels on two Sayma boards

· Assume laboratory temperature stability +/- 0.5 Celsius (C)

· Duration 24 hours

· Target performance

· ST3: SAWG to SAWG phase alignment variation < +/- 0.5 degree

· ST4: SAWG to TTL PHY alignment variation < +/-250 picosecond (ps)

C.3.1 CONTRACTOR QUALIFICATIONS

The Contractor shall possess a detailed understanding of the ARTIQ OS architecture and design including the following package dependencies misoc, migen, jesd204b (see repository links below). Prior contribution to the corresponding source repositories is the leading metric by which this requirement shall be judged.

C.3.1.2 The Contractor shall have had previous experience working closely with physical scientists as end customers. References may be requested from previous basic science collaboration work.

C.3.1.3 The Contractor shall have previously designed and demonstrated an FPGA-based SoC framework (FPGA system-on-chip), including integration of soft central processing units (CPUs), memory controllers, serial peripherals and Ethernet.

C.3.1.4 The Contractor shall have previously designed and demonstrated successful implementation of FPGA-based time-to-digital converter (TDC) devices with less than fifty (50) picosecond (ps) jitter.

C.3.1.5 The Contractor shall have previously demonstrated successful implementation of the development of embedded digital electronics products for use in basic science research.

C.3.1.6 The Contractor shall have previously demonstrated successful implementation of long-term support of an open source project, spanning at least five (5) years.

C.3.2 DELIVERABLES

The Contractor shall provide a quote for a Firm-Fixed-Price Level of Effort (FFP-LOE) type contracting with an estimated 638 hours of labor for the duration of the period of performance in support of the Research and Development (R&D) tasks defined in Core Deliverables C.3.2.1, Extended Deliverables C.3.3.2, and monthly reporting as defined in C.3.3.3. The labor for this contract is limited; not all Extended Deliverables will be actionable under this contract. The Contractor shall track hourly labor expended on individual tasks.

The Contractor may commence work on Core Deliverable upon award of the Contract. The Contractor may not start work on tasks listed under Extended Deliverables without written authorization from the TPOC. The budgeted time for Core Deliverables is 300 hours. Any deviations from the budgeted time requires approval from the TPOC.

Deliverables shall be provided to ARL according to the following schedule. The ARO date will be noted in the final award document.

(*) The labor for this contract is limited; not all Extended Deliverables will be actionable under this contract.

C.3.2.1 Core Deliverables

Several Deliverables are core to the functionality of the Sayma v2.0 PCB and have highest development priority.

C.3.2.1.1 The Contractor shall provide baseline ARTIQ support for the Sayma_AMC PCB to include the following.

· Debug PCB power up as required.

· Boot tasks including JTAG, loading flash & FPGA; JTAG is a standard defined by the Joint Test Action Group

· Universal asynchronous receiver-transmitter (UART)

· Synchronous dynamic random-access memory (SDRAM)

· Ethernet

· I2C EEPROM, MAC address and board serial numbers, USB-FTDI

· I2C is a type of Inter-Integrated Circuit standard

· EEPROM is electrically erasable programmable read-only memory

· MAC address is media access control address

· USB-FTDI is an integrated circuit a product made by the FTDI company

· Clocking, including ARTIQ distributed real-time input-output (DRTIO) clock recovery

· ARTIQ Real-time input-output (RTIO) transceivers

· ARTIQ RTIO serializer-deserializer (SERDES) TTL PHY

· FMC connectors

· FMC is FPGA Mezzanine Card as defined by the industry group VITA 57

· Build infrastructure and packaging C.3.2.1.2 The Contractor shall provide baseline ARTIQ support for the Sayma_RTM PCB to include the following.

· Debug PCB power up as required.

· Boot tasks including slave serial loading of FPGA.

· Rear-transition module (RTM) clocking.

· Develop DRTIO for advanced mezzanine card (AMC) FPGA to RTM FPGA link.

· Serial peripheral interface (SPI) to the Analog Devices Inc integrated circuit HMC830.

· Analog front end (AFE) interfaces.

· Build infrastructure and packaging.

C.3.2.1.3 The Contractor shall provide support for BaseMod PCB to include the following.

· Attenuator shift register

· DRTIO control of radio-frequency (RF) switches using ARTIQ TTL PHYs C.3.2.1.4 Validate RF output using SAWG v1.0 This tests operation of SAWG as developed for Sayma v1.0 works on Sayma v2.0. It tests the following elements.

· Clocking of AD9154

· AD9154 is an Analog Devices Inc integrated circuit

· SYSREF syncing of DAC and JESD204b core

· JESD204B to AD9154

· JESD204B is a standard defined by the JEDEC Solid State Technology Association

· SAWG v1.0 integration C.3.2.1.5 SAWG v2.0

· Ensure passage of tests ST1, ST2, ST3 and ST4 C.3.2.1.6 Stub Port

· Stub port of ARTIQ for the Sayma v2.0 PCB with focus on FPGA.

C.3.2.1.7 Design review

· Review of FPGA connectivity for the Sayma v2.0 PCB.

C.3.2.2 Extended Deliverables C.3.2.2.1 SAWG v2.0 element: 1 giga-sample per second (GSPS) Support SAWG v2.0. Develop code for Sayma v2.0 SAWG+JESD+FPGA clock tree at 1 GSPS FPGA sample rate.

C.3.2.2.2 SAWG v2.1 Elements C.3.2.2.2.1 Resource usage Measure resource usage and limit number of channels if unable to fit.

C.3.2.2.2.2 250 MHz clocking Evaluate clocking SAWG or parts of it at 250 MHz (2 times the ARTIQ RTIO clock)

C.3.2.2.2.3 Transaction-based SAWG RTIO Design transaction based SAWG RTIO protocol. Rewrite protocol to stage interpolator settings over one or few non-concurrent RTIO output channels, then activate synchronously with a single RTIO output event. Discuss and determine data partitioning among interpolators and SAWG channels.

C.3.2.2.2.4 Fractional representation for spline interpolator Design fractional representation of high-order spline interpolator coefficients. For example, instead of 64 bits, use 16- bit denominator and 16-bit numerator for the 3rd order spline coefficient. This also allows getting rid of the SAWG clock stretcher that was never officially supported.

C.3.2.2.2.5 SAWG DUC

Evaluate SAWG digital up converter (DUC) redesign with 3-bit or 4-bit frequency and phase resolution based on multipliers instead of parallel CORDICSs. CORDIC is Cordinate Rotation Digital Computer

C.3.2.2.2.6 Modulation after spline interpolators Evaluate resource consumption of modulation ports after spline interpolators. Multiplicative for amplitude, additive and saturating for frequency and phase. No support for configurable clipping amplitude at modulation summing junctions. Clipping is always on.

C.3.2.2.2.7 Suppression of random output spikes Guaranteed well-defined behavior when SAWG is not in a well-defined state. For example, during core device boot and core device crashes.

C.3.2.2.3 Interpolator overflow Option to blank DAC outputs if any of the amplitude interpolators overflow.

C.3.2.2.4 ARTIQ analyzer support for SAWG

C.3.2.2.5 Extended documentation Technical discussion of SAWG DSP architecture and design choices. Includes annotated schematics.

C.3.2.2.6 RTM DRTIO

Replace ARTIQ SERWB subsystem with pure DRTIO.

C.3.2.2.7 SDRAM test suite

C.3.2.2.8 White Rabbit PLL integration Integration of the White Rabbit PLL into ARTIQ for DRTIO satellites and repeaters.

C.3.2.2.9 Empty.

C.3.2.2.10 Continuous Integration (CI) Documentation Document manual and automated continuous integration (CI) tests, hardware-in-the-loop infrastructure, document CI infrastructure and how to run CI tests, support Hardware Developer and TPOC in reproducing CI tests.

C.3.2.2.11 Document adding DRTIO PHY Create a pedagogical example to document how to add a DRTIO PHY following the following github Issue. https://github.com/m-labs/artiq/issues/270 C.3.2.2.12 Metlino Bring Metlino PCB functionality to the same level as the Sayma DRTIO master variant but with all micro-TCA management carrier hub (MCH) ports available.

C.3.2.2.13 DDMTD

Research and development in support of synchronization of Sayma v2.0 PCBs. Specifically, application of the Digital Dual Mixer Time Difference (DDMTD) technique to enable synchronization of digital to analog converter (DAC) outputs using ARTIQ Distributed Real Time Input Output (DRTIO).

C.3.2.2.14 HMC Chip Support HMC Chip Support: In support of the DAC clock rates 1.2GHz, 2.0GHz and 2.4GHz, conduct tests of the HMC830, HMC7043 and AD9154 integrated circuits.

C.3.2.2.15 Simple pattern generator Development and documentation of a fixed test pattern generator as a compile-time alternative to the SAWG gateware signal generator for Sayma. The test pattern shall consist of a 12-point cosine on odd channels and ramps with major carry toggles on even channels.

C.3.2.2.16 Low SFDR pattern generator Development and characterization of a high-efficiency sine-cosine generator based on a hybrid LUT and coefficient-based interpolation. Optimized for minimal BRAM, LUT, and DSP resource usage. Achieving > 100 dBc spurious-free dynamic range (SFDR). This is a standalone generator not integrated into SAWG.

C.3.2.2.17 Ethernet MiSoC GTH transceiver-based 1000BASE-X Ethernet.

C.3.2.2.18 Emergent tasks The Contractor shall recommend additional tasks in support of software development based on lessons learned subject to technical review by the TPOC. Any additional tasks related to this effort may be incorporated into the contract via a written modification to the contract which will be issued bilaterally C.3.2.3 Support Activities The Contractor shall provide the following as required for the performance of this contract:

· shipping of PCBs to Hardware Developer and Timing and Integration

· rental of test and measurement equipment

· electronic components needed for hardware-in-the-loop automated testing, including 1 (one) Red Pitaya

· electronic components for PCB rework C.3.2.4 Progress Reporting

C.3.2.4.1 The Contractor shall provide the Government with monthly progress reports, which shall be, at minimum, two (2) typewritten pages, and consist of a detailed account of each month’s progress (budgeted hours, hours consumed), summary of code review and test results and planned work for the coming month. Monthly progress reports shall be submitted by the Contractor no later than the first (1st) of each month and in accordance with Data Item A001 on the DD FORM 1423.

C.3.2.4.2 Throughout the design phase of the requirement, the Contractor shall participate in email, email listings, and teleconferences.

C.3.3 TECHNICAL REQUIREMENT SPECIFICATIONS

The Contractor shall ensure that the requirements in Section 3.2 “Deliverables” meet the following specifications:

C.3.3.1 All code shall be covered with unit tests to at least 95% accuracy to verify functionality and to guard against regressions from future refactoring, extension, and/or bug fixes.

C.3.3.2 All code shall be supplemented by software test benches that enable simulation and unit testing without the need for hardware. Hardware test benches shall be detailed as such and must run on the relevant hardware with minimal manual intervention.

C.3.3.3 All classes shall include in-line documentation, including a high-level statement explaining how the code fits into the broader ARTIQ infrastructure.

C.3.3.4 All code exposed to the user shall be documented fully in-line and discussed in ARTIQ on-line documentation.

C.3.3.5 All code shall be platform independent where possible. Code sections that are not platform independent shall be clearly flagged as such.

C.3.3.6 The Contractor is responsible for obtaining all prototype hardware, tools and other resources as required to fulfil the obligations of this contract unless otherwise specified.

C.3.3.7 All project software and gateware shall be maintained in a suitable repository to allow introspection by ARL in order to monitor the progress of development and provide rapid feedback, as needed. The Contractor shall organize all code in a manner that may be reviewed by ARL regularly and as needed. The results of these reviews shall be integrated in subsequent development.

C.4 DISTRIBUTION STATEMENT

C.4.1 Determination of the PWS Document:

Distribution Statement A: Approved for public release. Distribution is unlimited.

C.4.2 Determination for information generated from the Contract:

Distribution Statement A: Approved for public release. Distribution is unlimited.

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