STATEMENT OF WORK.pdf

Statement of Work for the development of SESAR-LITE’s Firmware

Arlington Micro Systems, LLC. shall design firmware for SESAR-LITE’s radar processor . The firmware design shall target SESAR-LITE’s RFSoC-based processor and should implement multi-channel (12 channels or higher) reconfigurable radar processing functions as specified below. The company will also support thermal and radiation testing of the SESAR-LITE processor to evaluate firmware.

1. The firmware design shall implement phase locked clock synthesis, waveform synthesis, data acquisition, control signals, and other radar specific processing functionalities.

2. The firmware shall provide handshake, triggering, and synchronization across two identical boards and implement high throughput data transfers to a storage device.

3. The two boards shall support a minimum of 12 independent transmit and receive channels and include clock synthesis phased locked to external reference, and time tagging and stamping of the data.

4. The arbitrary waveform synthesizer shall support:

2.1 Liner Frequency Modulation (LFM) with up to 100-MHz bandwidth for 12 independent phase-locked to the external reference (e.g., 10 MHz).

2.2 Pulse lengths up to 60 s

2.3 Precise phase synchronization among all transmit channels.

2.4 Precise start of pulse synchronization among all transmit channels

2.5 Waveform synthesis reconfigurability by two means: a) uploading pre-generated arbitrary waveforms, and b) implementing on-board direct digital synthesis (DDS) with predefined (stored) waveform parameters.

5. The data acquisition shall support:

5.1 Selection of “raw” or “based band” In phase and Quadrature demodulation (I&Q),

5.2 FIR filtering and decimation with selectable decimation factor.

6. The firmware design shall include the generation of radar control logic signals (trigger, gating, switching logic, etc…) and the appropriate interface circuitry to the drive 12 T/R modules (per board) . Timing diagrams and description of these signals will be provided by NASA during development.

7. The firmware design shall implement Radar specific processing functionality including:

7.1 Pre-distortion of waveforms

7.2 Pulse Compression (as specified by NASA during development)

7.3 Beamforming (as specified by NASA during development)

7.4 Additional requirements specified by NASA during development

8. The design shall implement high throughput data transfers to a destination specified by NASA during the design stage.

9. The design shall be compatible with a connectorized enclosure specified by NASA that will house the boards. Mechanical requirements like enclosure size, connector placements will be specified by NASA.

10. The design shall be tested using loop-back test, emulated channel, and emulated targets.

II. Period of Performance

The Period of Performance is from 7/1/2023 and continues for twelve (12) months.

III. Deliverables

Arlington Micro Systems, LLC shall provide monthly progress reports throughout the period of performance. In addition, the company will deliver:

Quarter 1:

White paper on firmware conceptual design.

Report on conceptual design for peer review with NASA*.

Quarter 2:

Demonstration of Waveform Synthesis Design and Data Acquisition including test data captured with lab equipment and in Loop-back mode.

Documented test results*

Quarter 3

Demonstration of Pulse Compression implementation including test data captured with lab equipment and in Loop-back mode.

Documented test results*

Quarter 4

Demonstration of Pulse Compression driven Beamforming implementation including test data captured with lab equipment and in Loop-back mode.

VHDL or Verilog firmware project

Demonstration and testing of firmware compilation with NASA personnel using Xilinx tools.

Provide up to 100 hours of support for the thermal and radiation testing of the SESAR- LITE processor and evaluate performance of firmware under environmental conditions.

Final Documentation*

*Reports shall be created in Microsoft Word or PowerPoint formats.