RFI-JSL-2651-8102026_PMIC.pdf

Jet Propulsion Laboratory California Institute of Technology

4800 Oak Grove Drive Pasadena, California 91109-8099

August 19, 2026 Attn: Prospective Subcontractor

Subject: Request for Information (RFI) No. JSL-2651-8102026 for Power Management

Integrated Circuits (PMIC) for Aerospace Applications

The California Institute of Technology’s (Caltech’s) Jet Propulsion Laboratory (JPL), located at 4800 Oak Grove Drive, Pasadena, CA 91109, is issuing the subject RFI to obtain information to assess current industry manufacturing and technical capabilities and receive ROM cost and schedule estimates supporting the development of Power Management IC (PMIC) suitable for NASA space missions.

The requested information is for preliminary planning purposes only and does not constitute a commitment, implied or otherwise, that JPL will solicit you for such a procurement in the future.

Neither JPL nor the Government will be responsible for any costs incurred by you in furnishing this information.

Prospective subcontractors are advised that any information provided shall be deemed to be furnished with unlimited rights to JPL, with JPL assuming no liability for the disclosure, use or reproduction of such data. Please do not include any restrictive data or include restrictive marking. Any information submitted with restrictive marking will not be reviewed and returned.

Purpose

NASA's Ignition initiative (announced March 24, 2026) and High-Performance Space Computing (HPSC) program represent a fundamental shift toward sustained infrastructure operations with standardized, reusable platforms at continuous cadence. This transition from custom, one-off spacecraft designs to permanent lunar bases, commercial transportation systems, and “Science as a Service” missions drives the need for Power Management Integrated Circuits

(PMIC).

The purpose of this RFI is to gather information which could eventually lead to an RFP soliciting the development of one or more PMIC optimized for space applications for both commercial industry and government organizations.

Overview

NASA's Ignition initiative and the High-Performance Space Computing (HPSC) program are driving a strategic shift from traditional one-off spacecraft designs toward standardized, reusable, and sustainable space platforms. These programs emphasize long-duration infrastructure, such as lunar surface operations, commercial cislunar transportation, and persistent science platforms, all of which require reliable, compact, and power-efficient electronics capable of operating in harsh space environments.

Power Management Integrated Circuits (PMICs) are critical enablers for these next-generation systems. Highly integrated commercial PMICs currently available provide excellent integration, efficiency, and configurability for terrestrial and airborne applications. However, these devices generally lack the radiation hardness, reliability, and environmental resilience required for NASA missions.

Similarly, while some radiation-tolerant power solutions exist, there remains a significant gap in highly integrated, multi-rail, programmable PMICs specifically optimized for modern space-grade processors, FPGAs, and mixed-signal payloads.

This RFI seeks to understand industry capabilities to bridge this gap by developing one or more advanced space-grade PMICs that combine the integration density and flexibility of modern commercial solutions with the radiation performance and mission assurance required for NASA applications.

JPL is particularly interested in scalable architectures that can support a wide range of missions, from Low Earth Orbit (LEO) to deep space, while significantly reducing Size, Weight, and Power (SWaP), component count, and overall system complexity.

PMIC Specifications

1. Regulator Architecture & Channels

Synchronous Buck Converters (SMPS): Count: 4 to 8+ channels.

o Configuration: Configurable multi-phase operation (up to 10A+ total capacity).

Linear Regulators (LDOs):

o Count: 10 to 30+ channels.

o Performance: Low-noise, high-PSRR options for noise-sensitive rails.

Specialized Rails: Integrated support for Load Switches, VTT (DDR termination), and optional Boost converters as required.

2. Electrical Output Capabilities

Parameter Buck Converters LDOs

Output Voltage Range

0.25V to 3.6V Configurable based on load

Voltage Step Size Fine-tuning via 5mV to 10mV steps Fine-tuning capability

Parameter Buck Converters LDOs

Current Capacity 1A to 5A+ per rail Hundreds of mA per rail

Peak Efficiency >90% to 95% N/A

Voltage Scaling Dynamic Voltage Scaling (DVS) via

I2C / SPMI

Fixed or dynamically adjusted

3. Electrical Input & Protection

Input Voltage Range: Wide input support from 2.5V to 5.5V, with extended compatibility up to 21V to accommodate various system bus voltages.

Hardware Protection: Under-Voltage Lockout (UVLO) o Over-Voltage Lockout (OVLO) o Over-Current Protection (OCP) & Short-Circuit Protection o Over-Temperature Protection (OTP) with thermal shutdown

4. System Control & Power Sequencing Sequencing: Fully programmable power-up and power-down sequencing.

Control Signals: Dedicated Power-Good (PGOOD) signals and independent Enable (EN) pins.

Power States: Multiple operational modes including Active, Sleep, and Low-Power states.

Configurable I/O: 6 to 10+ GPIOs or multiplexed pins for system flexibility.

5. Diagnostics & Housekeeping Telemetry: Integrated ADC for real-time voltage, current, and temperature monitoring.

System Health: Hardware watchdog timer, fault interrupt generation, and fault logging registers.

Timing: Integrated Real-Time Clock (RTC) and crystal oscillator support.

6. Communication & Configuration Interfaces Control Interfaces: I2C, SPMI, or SPI for real-time configuration and telemetry access.

Non-Volatile Memory: Integrated One-Time Programmable (OTP) memory for storing default power-up states and custom boot configurations.

7. Advanced & System-Level Features

Power Management: Optional integrated battery and charger management for systems featuring energy storage.

EMI Mitigation: Spread-spectrum clocking to minimize electromagnetic interference.

Peripheral Support: Audio CODEC support or other co-located peripheral management as required by the application.

Power Consumption: Ultra-low quiescent current (Iq) during sleep modes to maximize system mission life.

Requested Information

To identify potential subcontractors, NASA seeks the information below:

1. PMIC Capabilities Describe how the PMIC specifications will be met and any expected deviations. Provide sample technical specifications—including Size, Weight, and Power (SWaP) estimates, efficiency targets, and rail counts—for the following mission classes:

Class A (CubeSat / Short-duration LEO): 4–8 channel SMPS, 10+ LDOs, < 1-year mission duration, Commercial-Off-The-Shelf (COTS) or radiation-tolerant approach.

Class B (Deep Space / Long-duration): High-reliability multi-phase bucks (up to 10A+), 20+ low-noise LDOs, fault logging, deep space environment, 10-year mission duration.

Class C (Human-Rated / Infrastructure): Highly configurable multi-channel PMIC architecture, telemetric ADC, advanced sequencing, I2C/SPMI control, lunar base or space station environment, 10+ year mission duration.

2. ROM (Rough Order of Magnitude) Cost and Schedule Estimates Provide Non-Recurring Engineering (NRE) and Recurring Engineering (RE) per-unit cost estimates targeting the different mission classes outlined above. Include an estimated development timeline from contract award to the first delivery of both engineering/lab models and flight-qualified units.

3. Capabilities and Approach Identify your ability to provide radiation-hardened, flight-grade PMICs (supporting TID and SEE mitigation). This includes detailing your approach to:

High-reliability packaging, semiconductor manufacturing, quality assurance, and testing suitable for human-rated aerospace environments.

Silicon-level configuration capabilities, including integrated One-Time Programmable (OTP) memory management and firmware/software tools for telemetric monitoring.

Key lower-tier subcontractors (e.g., foundries, packaging houses, or testing facilities) necessary to design, fabricate, and deliver the final product.

4. Funding Discuss the potential for cost-sharing versus the need for NASA Non-Recurring Engineering (NRE) support and provide an estimate for the required level of funding support.

Additional Information

Please provide the requested information by August 31, 2026 via email to:

JPL Technical Manager, Greg Carr at Gregory.A.Carr@jpl.nasa.gov JPL Acquisition Division personnel, Jane Lee at Jane.Lee@jpl.nasa.gov

If you have any questions about this RFI, please contact the undersigned.

Sincerely, Jane Lee Group Supervisor, Acquisition Division Office: 818-354-1586 | Mobile: 818-928-9581 4800 Oak Grove Drive Pasadena, CA 91109-8099