HR001117S0054.pdf

HR001117S0054

Microsystems Technology Office Broad Agency Announcement

Electronics Resurgence Initiative: Page 3 Investments Design Thrust

HR001117S0054

September 13, 2017

Foreword In his seminal 1965 paper, Gordon Moore, one of the pioneers of the ongoing microelectronics revolution, famously predicted a trajectory of progress in which the transistor count of integrated circuits would double every two years while the cost per transistor would decrease1. This projection became known as Moore’s Law. It set the electronics industry on a quest for continued scaling for more than 50 years and those who have mastered the technology have enjoyed the greatest commercial benefits and the greatest gains in defense capabilities. However, it is clear that the design work and fabrication now required to keep pace is becoming increasing difficult and expensive. The current trajectory of scaling has strained both the commercial and defense sectors, as much for economic as for technical reasons.

From a national security perspective, the dynamics that resulted from Moore’s observations and analysis have become increasingly complex. The Department of Defense (DoD) has ridden the relentless wave of technical progress in electronics to create exceptionally complex and high-performance systems. However, the current cost of development is challenging the national security enterprise. The rate of development of novel and unique electronics, based on advances in fundamental science and engineering research, has dwindled within the DoD. The number of leading-edge manufacturing sites that are considered a part of the national security enterprise is diminishing, and the fundamental tie between national security and the health of the electronics industry is strained. The shift in focus of all major electronics entities has been towards large-volume global supply chains as a means to manage the dynamics and economics of scaling. But this has also made it more difficult for the DoD to leverage industry capabilities for the small-volume, high-performance technology that the defense sector needs. With the Electronics Resurgence Initiative (ERI), DARPA seeks to address these imbalances, ultimately working hand-in-hand with industry to embrace the coming inflection in Moore's Law. The goal of the ERI is to more constructively enmesh the technology needs and capabilities of the defense enterprise with the commercial and manufacturing realities of the electronics industry.

1 G. E. Moore, "Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114," in Proceedings of the IEEE, vol. 86, no. 1, pp. 82-85, Jan. 1998.

doi: 10.1109/JPROC.1998.658762 <https://doi.org/10.1109/JPROC.1998.658762>

Electronics Resurgence Initiative (ERI)

During these unique times, it is instructive to read all of Moore’s prescient paper. On page two, he laid out what became his famous projection for scaling transistor count. However, on page three, with an eye toward the times we now live in, he laid out the technical directions to explore when the conditions under which scaling will be the primary means for advancement are no longer met. A trio of simultaneously-released ERI BAAs—this one among them—parallel the research areas detailed on page three of Moore’s paper: materials and integration, architecture, and design. These new page-three-inspired investments, along with a series of related investments from the past year, comprise the overall Electronics Resurgence Initiative.

The “ERI Page 3 Investments” are the next steps in creating an electronics capability that will provide a foundational contribution to U.S. national security. They reflect a collaborative spirit that we hope will lead an electronics industry capable of meeting its own commercial needs and ambitions while simultaneously advancing national defense in the 2025 to 2030 time frame.

DARPA is eager to receive proposals from entities that can further the broader cause of the electronics industry while simultaneously embracing national security, based on the development and consistent availability of advanced, high-performance electronics technologies.

ERI Page 3 Investments Overview

Table of Contents

Foreword

PART I: OVERVIEW INFORMATION

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description A. Background B. Page 3 Design Description C. The Intelligent Design of Electronic Assets (IDEA) Program

1. Program Background

2. Program Structure

3. TA-1: Machine Generated Physical Layout

4. TA-2: Intent Driven System Synthesis

5. Schedule and Milestones

6. Program Deliverables

7. Government Furnished Information

D. The Posh Open Source Hardware (POSH) Program

1. Program Background

2. Program Structure

3. TA-1: Hardware Assurance Technology

4. TA-2: Open Source Hardware Design Technology

5. TA-3: Open Source System-on-Chip Demonstration:

6. Schedule and Milestones

7. Program Deliverables

II. Award Information A. General Award Information B. Fundamental Research

III. Eligibility Information A. Eligible Applicants

1. Federally Funded Research and Development Centers (FFRDCs) and Government Entities

2. Non-U.S. Organizations and/or Individuals B. Organizational Conflicts of Interest C. Cost Sharing/Matching D. Other Eligibility Criteria

1. Collaborative Efforts IV. Application and Submission Information

A. Address to Request Application Package B. Content and Form of Application Submission

1. Full Proposal Format

2. Proprietary Information

3. Security Information

a. Unclassified Submissions

4. Disclosure of Information and Compliance with Safeguarding Covered Defense

Information Controls

5. Human Research Subjects/Animal Use

6. Approved Cost Accounting System Documentation

7. Section 508 of the Rehabilitation Act (29 U.S.C. § 749d)/FAR 39.2

8. Grant Abstract

9. Small Business Subcontracting Plan

10. Intellectual Property

a. For Procurement Contracts

b. For All Non-Procurement Contracts

11. Patents

12. System for Award Management (SAM) and Universal Identifier Requirements

13. Funding Restrictions

C. Submission Information

1. Submission Dates and Times

a. Full Proposal Date

b. Frequently Asked Questions (FAQ)

2. Proposal Submission Information

a. For Proposers Requesting Grants or Cooperative Agreements:

b. For Proposers Requesting Contracts or Other Transaction Agreements

c. Classified Submission Information

V. Application Review Information A. Evaluation Criteria

1. Overall Scientific and Technical Merit

2. Potential Contribution and Relevance to the DARPA Mission of Supporting

National Security

3. Impact on the Overall Electronics Landscape

4. Cost Realism

B. Review and Selection Process

1. Review Process

2. Handling of Source Selection Information

3. Federal Awardee Performance and Integrity Information (FAPIIS)

VI. Award Administration Information A. Selection Notices

1. Proposals B. Administrative and National Policy Requirements

1. Meeting and Travel Requirements

2. FAR and DFARS Clauses

3. Controlled Unclassified Information (CUI) on Non-DoD Information Systems

4. Representations and Certifications

5. Terms and Conditions

C. Reporting D. Electronic Systems

1. Wide Area Work Flow (WAWF)

2. i-Edison

3. Contract Execution Reporting Service (CERS)

VII. Agency Contacts VIII. Other Information

A. Proposers Day B. Protesting

ATTACHMENT 1: Cost Volume Proposer Checklist ATTACHMENT 2: Proposal Summary Slide Template

PART I: OVERVIEW INFORMATION

Federal Agency Name: Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO)

Funding Opportunity Title: Electronics Resurgence Initiative: Page 3 Design Announcement Type: Initial Announcement Funding Opportunity Number: HR001117S0054 Catalog of Federal Domestic Assistance Numbers (CFDA): 12.910 Research and

Technology Development Dates: (All times listed herein are Eastern Time) o Posting Date: September 13, 2017 o Proposers Day: September 22, 2017 o FAQ Submission Deadline: 1:00 PM on November 1, 2017 o Proposal Due Date: 1:00 PM on November 14, 2017 o Estimated period of performance start: May 2018

Concise description of the funding opportunity:

DARPA is soliciting innovative research proposals in the area of physical design of electronic circuits and systems. Proposed research should investigate innovative approaches that enable revolutionary advances in science, devices, or systems.

The Design thrust of the Electronics Resurgence Initiative (ERI): Page 3 Investments will address today’s System-On-Chip (SoC) design complexity and cost barriers, creating the environment needed for the next wave of US semiconductor innovation. Programs within this thrust will develop the algorithms and software required to realize a unified layout generator that will enable fully automated “no human in the loop” physical design of SoCs, system-in-packages (SiPs), and printed circuit boards (PCBs) in 24 hours. In parallel, programs will create the building blocks, validation methodologies, and infrastructure required for a scalable open source hardware ecosystem, bringing best practices in software to hardware design.

Anticipated individual awards: Multiple awards are anticipated Anticipated funding type:

o IDEA: 6.1 and 6.2 o POSH: 6.2

Types of instruments that may be awarded: Procurement contract, grant, cooperative agreement or other transaction.

Agency contact:

o Andreas Olofsson, Program Manager

BAA Coordinator: HR001117S0054@darpa.mil

DARPA/MTO

ATTN: HR001117S0054

675 North Randolph Street Arlington, VA 22203-2114 mailto:name@darpa.mil

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description

The Defense Advanced Research Projects Agency (DARPA) often selects its research efforts through the Broad Agency Announcement (BAA) process. This BAA is being issued, and any resultant selection will be made, using the procedures under Federal Acquisition Regulation (FAR) 6.102(d)(2) and 35.016 and 2 C.F.R. § 200.203. Any negotiations and/or awards will use procedures under FAR 15.4, Contract Pricing, as specified in the BAA (including DoDGARS Part 22 for Grants and Cooperative Agreements, and Part 37 for Technology Investment Agreements).

Proposals received as a result of this BAA shall be evaluated in accordance with evaluation criteria specified herein through a scientific review process.

DARPA BAAs are posted on the Federal Business Opportunities (FedBizOpps) website, http://www.fbo.gov/, and, as applicable, the Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA.

The Microsystems Technology Office at DARPA seeks innovative proposals in the areas of physical design and verification that will enable rapid specialization of SoCs. It is anticipated that research with the Electronic Resurgence Initiative Design thrust will create modular software for completely automated physical design of electronic circuits and an open source hardware ecosystem through creation of open source “Intellectual Property” circuit and validation technology. Research within this program is expected to drastically reduce the cost and design time of PCBs, SiPs, and integrated circuits. Proposed research should investigate innovative approaches that enable revolutionary advances in science, devices, or systems.

A. Background

Next-generation intelligent systems supporting Department of Defense (DoD) applications in artificial intelligence, autonomous vehicles, shared spectrum communication, electronic warfare, and radar will require processing efficiency orders of magnitude better than what is offered by current commercial electronics. Reaching the performance levels required by our Nation’s needs will require development of highly complex SoC platforms leveraging the most advanced integrated circuit technologies. Unfortunately, as the complexity of chips has rapidly increased in line with Moore’s law predictions, recent years have seen an explosion in the cost and time required to design advanced SoCs, PCBs, and SiPs, as illustrated in Figure 1. To fully unlock innovation and maintain the DoD’s technical superiority, the Page 3 Design thrust will develop new paradigms for intelligent physical design and reduce the barriers to design of high-performance, high-efficiency custom integrated circuits.

http://www.fbo.gov/ http://www.grants.gov/

Figure 1. Illustration of the rapid increase in resources required for physical design and verification as Moore's Law has progressed.

The barriers facing the physical design of integrated circuits today parallel some of the challenges faced by chip designers nearly three decades ago. At that time, high costs and difficult access associated with chip fabrication presented a severe bottleneck to prototyping of novel circuits and designs by research institutions. To remove the fabrication barriers that were inhibiting semiconductor innovation, DARPA developed the Metal Oxide Semiconductor Implementation Service (MOSIS) program. MOSIS enabled cost-effective prototyping of chips through multi-project wafer runs. Supported by strong industry demand, the successful MOSIS program launched the fabless electronics industry and led to a wave of US semiconductor innovation.

Like MOSIS, the Page 3 Design thrust will foster the environment needed for the next wave of U.S. semiconductor innovation. Through creation of a software-based, “no human in the loop” physical layout generator and an open source Intellectual Property (IP) eco-system, the Page 3 Design thrust will usher in an era of 24-hour design for DoD hardware systems, shorten upgrade cycles, and enable wide proliferation of commercial and DoD-specific SoCs. The Page 3 Design thrust will encompass two programs, the Intelligent Design of Electronic Assets (IDEA) and Posh Open Source Hardware (POSH).

B. Page 3 Design Description

The Page 3 Design thrust includes two programs that will operate independent of each other:

Intelligent Design of Electronic Assets (IDEA): “No human in the loop” 24-hour layout generation for mixed signal integrated circuits, systems-in-package, and printed circuit boards.

Posh Open Source Hardware (POSH): An open source System on Chip (SoC) design and verification eco-system that enables cost effective design of ultra-complex SoCs.

When proposing to multiple programs, proposers are required to propose solutions for IDEA and/or POSH in separate proposals. Proposers should not propose to more than one program in a single proposal. Further information about the programs can be found in Section C (IDEA) and Section D (POSH).

C. The Intelligent Design of Electronic Assets (IDEA) Program

1. Program Background

Today’s typical physical design flow consists of multiple phases implemented by moderate to large teams of physical designers using Computer Aided Design (CAD) tools as aids to perform chip floor-planning, device placement, routing, and physical verification. Despite commonalities between design flow steps in integrated circuits (ICs), SiPs, and PCBs, layout is completed using separate tools by design groups with minimal overlap. In the digital IC domain, layout automation has been integral to the design of complex circuits at advanced technology nodes, but progression towards full automation has now stalled. In the analog and board domains, physical design is still a largely manual process, preventing cost- and resource-efficient layout of truly complex mixed signal systems. Commercial electronics manufacturers of SoCs employ large teams of designers, each with expertise in a specific facet of the design flow to meet design requirements; however, DoD researchers and development teams do not have the resources available to effectively execute such a strategy, resulting in hardware design cycles of 12-36 months.

To overcome these limitations and keep pace with the exponential increases in SoC complexity associated with Moore’s law, the IDEA program aims to develop a fully automated “no human in the loop” circuit layout generator that enables users with no electronic design expertise to complete physical design of electronic hardware.

As shown in Figure 2, the IDEA layout platform will support automated physical layout of multiple types of electronic components, including analog and digital SoCs, SiPs, and PCBs. IDEA will develop the infrastructure, algorithms, methods and software required to successfully demonstrate “no human in the loop” physical layout, transforming a complete design netlist into a manufacturable layout database. It is envisioned that the IDEA platform will leverage applied machine learning methodologies to continuously evolve and improve performance as new data sets become available. The customization offered from training will empower differentiation through the breadth and quality of training sets available to the end user, providing specialized users with an asymmetric advantage benefiting from an existing database of designs. Through 100% automation of electronics layout, IDEA is expected to usher in a new era of 24-hour design of DoD hardware systems. It is anticipated that achieving the autonomy goals of the IDEA program will require breakthroughs in machine learning and optimization algorithms.

Figure 2. Illustrative design flow describing existing design practices and the components of physical layout that the IDEA unified physical design generator will complete.

2. Program Structure

The IDEA program includes two main Technical Areas (TAs). The Technical Areas are illustrated in Figure 3 and are described below:

TA-1: Machine Generated Physical Layout: Development of a unified physical layout generator for digital and analog SoCs, SiPs, and PCBs.

TA-2: Intent Driven System Synthesis: Development of an intent-driven, correct-by construction system generator.

Figure 3. A flowchart providing a high-level illustration of the IDEA technical areas. The figure indicates the formats the software is expected to support for digital and analog SoC, SiP and PCB physical design.

IDEA does NOT seek proposals for:

Investigatory research that does not deliver useful software Development of high level languages, compilers, and generators for Boolean logic design Architectures that simply reduce or remove the need for physical layout New manufacturing processes and technologies

Each technical area will contain multiple subtasks to which performers may propose solutions.

Proposals that address more than one IDEA technical area or multiple subtasks within a technical area must be constructed so that each subtask can be selected independently from one another.

Proposers who include multiple subtasks in their proposal should describe each subtask separately and should provide separate pricing for each subtask.

Due to the complexity of physical design, it is anticipated that performers will be developing software modules for individual portions of the design flow and working with other performers to create a complete IDEA TA-1 or TA-2 software design flow meeting the IDEA program metrics.

Close coordination among performers in all technical areas will be critical to program success.

Performers not proposing a complete solution will be required to collaborate with other performers and integrate modules into the software platform continuously throughout the program.

Integration exercises, one week in length, will be held twice a year in each phase for software integration and evaluation of the “no human in the loop” physical layout and system generators.

All IDEA performers will be required to attend and work with other performers during these integration exercises. Performers are also expected to adapt proposed algorithms and modules throughout the program to continuously optimize the performance of the unified physical layout generator and system generator. Given the importance of open interfaces and interoperability between software modules, proposals must include a one page long Collaborative Statement that describes (1) how the proposed work will be integrated within the IDEA design flow, (2) performer’s prior experience with open collaboration, (3) a declaration of any license and copyright restrictions imposed on the delivered software and intra-module Application Programming Interfaces (API), and (4) an affirmation, indicated by signature on the Collaborative

Statement document, that the proposer accepts the requirement to collaborate with other program performers as necessary to meet the overall program goals and objectives stipulated in the BAA and the proposer’s Statement of Work (SOW).

Program evaluation will be conducted by U.S. Government (USG)/Federally Funded Research and Development Centers (FFRDC) personnel. The evaluation effort will consist of physical design of a suite of government provided SoC, SiP, and PCB benchmarks and comparison of the power, performance and area against a physical layout completed using traditional techniques.

Evaluations will be conducted throughout each phase and at each integration exercise. Performers may continue from Phase 1 to Option Phase 2 based on software modification in response to technical feedback, evaluation at integration exercises, and end-of-phase evaluations conducted on the integrated software platform.

In addition to novel research, the program will emphasize delivery of working high quality software. Software modules created in the program are expected to be interoperable with modules developed by other program performers, and intellectual property rights asserted by proposers are strongly encouraged to be aligned with non-viral open source licenses such as the Apache 2.0, Massachusetts Institute of Technology (MIT), and Berkeley Software Distribution licenses. If a proposed approach includes proprietary software or technical data as a component of the approach, the proposer is expected to provide 1) clear justification for the need for the proposed software, and 2) a description of how the IDEA program goals will be met with use of the proprietary model.

3. TA-1: Machine Generated Physical Layout

The primary goal of IDEA TA-1 is to create and deliver a unified platform for completely automated layout generation of SoCs, SiPs, and PCBs. A notional IDEA layout generator framework is shown in Figure 4 and defines the critical design steps of the design flow from source input to physical deliverable. Proposers should note that the notional design flow architecture is provided for clarification and is expected to evolve over the course of the program. Performers may propose to develop automated software for one, multiple, or all identified subtasks, with the expectation that software modules will be integrated into the complete software platform throughout the program. IDEA TA-1 also encourages proposals from analog and digital design teams that will develop novel SoC designs and interact with TA-1 software developers to support evaluation of the IDEA physical design platform.

The critical research questions for this technical area are:

Can we achieve “no human in the loop” SoC, SiP, and PCB layout at advanced nodes?

To achieve “no human in the loop” layout, what power, performance, area (PPA) results should be targeted?

Can we demonstrate a layout platform that continuously improves with additional data from new designs and training sets?

What algorithms and machine learning techniques are best suited to achieving the goal of “no human in the loop” automation?

What design and CAD approaches are scalable to supercomputer and data-center size compute infrastructure?

What design methodologies and design infrastructure are needed for fully automated layout?

How can we completely decouple front end design details and EDA flows from proprietary foundry rules and models, such as process development kits (PDKs)?

Figure 4. A description of the notional IDEA TA-1 software framework, illustrating critical design flow subtasks and an outline of key characteristics. TA-1 performers may propose to develop software for some or all of the identified subtasks. The image is color coded to indicate whether the proposed software for the specified subtask must be applicable to chips only, or chips, boards and packages.

The software developed in IDEA TA-1 is expected to take standard design source files as inputs and produce complete GDSII databases ready for manufacturing. Specifically, the software platform is expected to produce complete layout databases using one or more of the following inputs: (1) unannotated netlists for analog IC designs, (2) Verilog Register Transfer Level (RTL) and instantiated fixed circuit primitives/macros circuit blocks for digital IC designs, and (3) structured Verilog netlists for SiPs and PCBs. The software platform will be evaluated against novel designs created by SoC designers as well as the government benchmark suite.

The overarching goal of TA-1 is to create a unified software platform capable of continuous improvement through training and experience that meets the program metrics as identified in Table

1. It is anticipated that development of such a platform will be an extensive collaborative endeavor, and program performers may propose to develop software modules for portions of the design flow that will be integrated into the final software platform. In addition to novel research, all TA-1 performers will be required to work collaboratively to define the required standards, open interfaces, and design methodology needed to build a seamless, publicly releasable platform for layout generation of SoCs, SiPs, and PCBs. Performer software modules will be evaluated both individually and as part of the physical layout generator platform. TA-1 deliverables will be verified through layout of a set of openly available government furnished benchmark circuits. The following list gives an indication of the types of benchmarks that may be included in the government furnished benchmark suite:

OpenPiton (http://parallel.princeton.edu/openpiton/#infosec) RISC-V Rocket chip (https://github.com/freechipsproject/rocket-chip) BeagleBone (https://beagleboard.org/black) Facebook Wedge Board (https://opencompute.org) BaseJump Wirebond Ball Grid Array (BGA) package (http://bjump.org/)

Table 1. TA-1 metrics by phase. Relative PPA is PPA referenced to SoC benchmarks created with traditional design flow techniques.

Technical Area Metrics Phase 1 Phase 2

SoC Benchmarks Government furnished benchmarks

14nm CMOS PDK

Government furnished benchmarks

7nm & 14nm CMOS PDK

Board Benchmarks BeagleBone Black1 Open Compute Server2

SiP Benchmarks Government furnished benchmarks

Government furnished benchmarks

Benchmark PPAIDEA/PPATraditional

(3)

0.5 1

Package Complexity Up to 2 die, 2.5D Up to 1024 die, 2.5D

Automation 100%

Turnaround time 24 hours

IDEA TA-1:

Machine

Generated Physical Layout

Deliverable Software, license4, software documentation 1This metric is a measurement of functional equivalence to a BeagleBone Black circuit card.

2This metric is a measurement of functional equivalence to an Open Compute Server.

3Relative Power, Performance, Area (PPA) as compared to benchmark layout completed by a small physical design team using off-the-shelf tools current to 2017 commercial EDA ideology. Higher numbers indicated higher quality with “1” being the current status.

4Delivered with a minimum of government purpose rights; open source licenses are preferred.

The physical layout generator developed in TA-1 is expected to support existing state of the art design techniques, including but not limited to:

Analog, digital, and mixed signal design Asynchronous and synchronous digital design styles http://parallel.princeton.edu/openpiton/#infosec https://github.com/freechipsproject/rocket-chip https://beagleboard.org/black https://opencompute.org/ http://bjump.org/

Clock gating Automated pipeline retiming Multiple clock domains Multiple voltage domains Power gating and adaptive voltage scaling Scan insertion Physical design hierarchy Large designs (>100M placed instances) Flip-chip, micro-bumps, and wire-bond packaging 2.5D Systems-in-Package Advanced PCB manufacturing technologies, consistent with technologies used for 2017 smartphone manufacturing

Phase 1: Exploratory Research [Base – 24 months] In Phase 1 of TA-1, performers are expected to develop new concepts and collaborate with other TA-1 performers to create and integrate software modules into a completely automated layout generator that achieves 50% of the PPA target of existing human-centric EDA flows. This includes:

1. Codifying state of the art designer knowledge

2. Demonstrating pathways to apply machine learning to physical design and creation of annotated datasets for machine learning

3. Collaborating on IDEA standards and APIs

4. Developing software modules within the IDEA automated layout generation pipeline

5. Delivering alpha, beta and public versions of modules developed in Phase 1 for completely automated back-end physical design. Software should support physical design at multiple technology nodes, including 14nm, 28nm, 65nm, and 180nm

CMOS.

Phase 2: Optimization and System Demonstration [Option – 24 months] In Phase 2 of TA-1, performers should extend concepts developed during Phase 1 with the goal of reaching a performance of 100% PPA compared to existing resource limited human-centric design flows used to layout the benchmark circuits provided by the USG/FFRDC. This includes:

1. Advancing the state of the art in machine learning to leverage a diverse set of strategies and algorithms to optimize performance on a per circuit basis.

2. Extending module applicability to support newer CMOS technology nodes, including 7nm, while maintaining applicability to 14nm, 28nm, 65nm, and 180nm nodes.

3. Training the physical design platform on expanded datasets and redesigning Phase 1 benchmark circuits at 14nm node to demonstrate PPA improvements achieved through additional learning.

4. Delivering stable versions of the IDEA software modules appropriate for large user scale deployment.

5. Increasing the number of IDEA platform users to ensure successful software transition at the end of the program.

A list of the TA-1 subtasks that proposers are encouraged to address is provided in Table 2.

Proposers are expected to develop or use existing data to create the required training models; data will not be supplied by the USG/FFRDC. Unless otherwise specified in the Description column of Table 2, proposed solutions are expected to support analog and digital SoCs, SiPs and PCBs. For example, a proposed solution for an automated routing software module should support routing for digital ICs, analog ICs, SiPs and PCBs; a proposed automated router that only supports digital IC design is not within scope. If a proposal addresses a design step not identified in Table 2, a thorough technical justification must be provided discussing the need for the module and relevance to successful creation of an automated physical design flow.

Table 2. Table identifying and describing subtasks proposers may propose to as part of IDEA TA-1.

Performers may propose solutions for one or multiple of the identified subtasks.

TA-1 Subtask Description

Databases / Processing

Create critical infrastructure for TA-1 performers, including but not limited to: distributed and in-memory design databases, infrastructure for distributed EDA computing on data-center and supercomputer scale computers.

Cloud infrastructure

Develop compute infrastructure, IP firewalling, and merchant eco-system needed to allow the “no human in the loop” IDEA layout generator to be effectively accessed as a cloud based software service by the broader community.

Timing Analysis

Full circuit and incremental scalable timing analysis software for synchronous and asynchronous circuits. Interacts with synthesis, floorplanning, placement, clock-tree synthesis, routing, and layout finishing sub-tasks through an open API.

Parasitic Extraction

Extraction technology, foundry-specific parasitic models for capacitance, resistance, inductances. Interoperable with all TA-1 software modules.

Readers + Writers

Optimized parsers, readers, writers for standard file formats such as Verilog, GDSII, LEF, DEF, SPICE, LIBERTY, SDC, and PDKs.

Common Infrastructure

Power and Signal Integrity

Analysis

Circuit power and signal integrity software with support for instantaneous dynamic power analysis, static power consumption, electro-migration, reliability, and thermal analysis. Interacts with synthesis, floorplanning, placement, clock-tree synthesis, routing, and layout finishing sub-tasks through an open API.

Logic Synthesis Transform Verilog RTL to a gate level netlist (digital circuits only).

Floor-planning Generate correct by construction floor-plans using structured netlists, PDK, minimal user constraints, and trained models as inputs.

Placement Place all cells/parts using floorplan, structured netlist, PDK, minimal user constraints, and trained models as inputs.

Layout Generators

Clock Tree Synthesis Synthesis and layout of a clock distribution network (digital circuits only).

Detailed Routing Route all nets in the design using placed circuit, PDK, minimal user constraints, and trained models as inputs.

Layout Finishing Design For Manufacturing optimizations using routed circuit, PDK, minimal constraints, and trained models as inputs.

Design SoC Design Advisors

Expert design teams that will act as advisors to the IDEA layout platform developers and use the IDEA software to demonstrate “no human in the loop” layout of an appropriate 100mm2 SoC at 14nm CMOS as well as accompanying package and board.

TA-1 performers will be encouraged to build software in a modular fashion and are expected to utilize standard read/write formats to ensure interoperability. Proposers should describe a strategy for contribution and maintenance of their software modules on an accessible platform and growth of the user community within the integrated software platform in their proposal. Performers will be encouraged to create repositories open to program collaborators and frequently release software modules developed throughout IDEA on an industry-standard, accessible software collaboration platform.

Also included in Table 2 is a subtask encouraging proposals from analog and digital design teams, “SoC Design Advisors”, to support the evaluation of the IDEA back-end physical design platform.

The Design Advisors are expected to design novel high performance SoCs for an identified application and use the IDEA platform to complete physical design of the SoC and associated package and board. Proposers should identify the application and pathways to performance improvement over today’s state of the art in the proposal. Proposers should leverage the wide variety of designs the IDEA platform will support, including analog and digital circuits and next generation packaging formats. DARPA will provide fabrication support for proposers to the SoC design team subtask through a number of separately funded multi-project or dedicated wafer runs;

therefore, fabrication costs should not be included in proposal budgets. As shown in Figure 6, proposers should assume an early Phase 2 tapeout will occur at a primary commercial foundry at the 14nm CMOS technology node and a later Phase 2 tapeout will occur at a primary commercial foundry at the 7nm CMOS technology node. Teams proposing to SoC Design Advisors will be expected to deliver SoC, packaging and board hardware at the end of Phase 2.

A selectable proposal for one or more subtasks of the IDEA TA-1 framework must include the following:

A description clearly stating whether the proposed software module supports a step in the IDEA design framework identified in Table 2

A description of the unique technical merits and value provided by the technology to meet the goals of the TA-1 as described above. Proposers may use prior work to argue the technical merits of their approach

A description of each proposed software module and its function A description of how proprietary PDK related data will be separated from the main layout generator and how communication with said model is handled.

A description of 1) the data the training models will be extracted from and 2) how proprietary trained “knowledge models” will be separated from the main layout generator and how communication with said model is handled.

A list of constraints for the software module, identifying the source of the constraints (whether from other software module or initial user input)

A full description of required design inputs, where applicable A full description of design outputs, where applicable A discussion of the plan to achieve autonomous functionality for the software module in the following regards:

o Autonomous operation – given inputs and constraints, produce output without human intervention o Autonomous handoff – condition outputs such that they can be used by other modules without human intervention A description of the proposer’s anticipated software release schedule o Public releases of software are required at the end of each phase o At a minimum, controlled releases should occur on an industry-leading collaborative development platform prior to each scheduled integration exercise.

Additional releases to facilitate integration are strongly encouraged

A description of appropriate mid-phase technical metrics applicable to the evaluation of the proposed software modules

4. TA-2: Intent Driven System Synthesis

Given a high-level functional description and minimal constraints, the software developed in IDEA TA-2 will create correct-by-construction PCBs and systems based on a vast library of Commercial Off The Shelf (COTS) components. Examples of COTS components include commercially available packaged chips for PCBs, bare die for SiPs, and IP modules for SoCs. The design netlist created by the TA-2 software will be fed into the layout generator developed in TA-1 to create an end-to-end automated design platform for PCBs, SoCs and SiPs.

Today’s design of complex systems is a largely manual process involving the following steps:

1. Creation of a text document describing functional specifications, power, area, performance, reliability, and cost constraints

2. Selection of a perceived optimal set of devices from a rich library of existing parts

3. Manual design of exact electrical schematic using said parts

4. Placement of components and routing of all nets and power connections

5. Manual review and simulation (optional)

IDEA TA-2 seeks to create software to replace steps 1-3 of the process above, while TA-1 creates automated software for step 4.

While purely Boolean circuits can be realized from a finite library of well understood combinatorial and sequential cells, complex PCB and SoC designs are realized from a much larger library of complex components, most of which cannot be represented by a simple mathematical model. Currently, there are over five million commercial COTS parts in circulation, with component descriptions embedded in text data sheets that require manual review, leaving no path to automated parts selection with a system generator.

A notional design flow architecture for IDEA TA-2 is illustrated in Figure 5. Proposers should note that the notional design flow architecture is provided for clarification and is expected to evolve over the course of the program. As illustrated, the backbone of the design flow is supported by creation of an open parts database with an extensive library of components to meet the extreme needs of the DoD. Performers may propose to develop automated software for one, multiple, or all identified subtasks, with the expectation that software deliverables will be integrated into the complete TA-2 software platform throughout the program. If a performer proposes a different design flow or a design step not identified in Figure 5, a thorough technical justification must be provided detailing why the module is required for successful creation of an intent driven system design platform for PCBs, SoCs and SiPs. Performers within each subtask are expected to work together and collaboratively develop the models required for the platform.

Figure 5. A notional design flow illustrating the IDEA TA-2 subtasks: 1) an open parts database, 2) a system generator consisting of high level system design entry and a reference design generator, and 3) a circuit optimizer.

The TA-2 technical work consists of three sub-tasks:

1) 5M+ Open Parts Database: Development of an expansive library (with the capacity to support data for more than five million entries) of appropriately modeled COTS parts supporting PCBs, SiPs and SoCs for use by the schematic generator and optimization tools developed in IDEA TA-2. The library should support a large diversity of components including, but not limited to, microcontrollers, DRAM, ADCs, DACs, PMICs, IO interfaces, passive devices and connectors. It is anticipated that this task will involve automated data mining of the large corpus of open datasheets and documentation associated with COTS parts currently in distribution.

2) System Generator: Creation of methodologies for high level system design entry, and development of a system generator that creates a selection of known good structured Verilog netlists based on user provided intent-based descriptions.

3) Circuit Optimizer: Development of a circuit optimizer that takes structured generic Verilog netlists as an input and produces an optimized design based on criteria such as size, weight, power, cost, reliability, and system standard compliances.

IDEA TA-2 performers will be required to work with other performers in TA-2 to define the required set of standards, open interfaces, and techniques necessary to build seamless, publicly releasable software necessary to meet the TA-2 program metrics specified in Table 3. Performer software modules will be evaluated both individually and as part of the physical layout generator platform. TA-2 deliverables will be verified through layout of the benchmark boards specified in Table 3.

Phase 1: Exploratory Phase [Base – 24 months] In the exploratory phase of TA-2, performers are expected to demonstrate new concepts and work with other TA-2 performers to create a complete high-level system synthesis platform for SoCs, SiPs and PCBs. Within Phase 1, performers are expected to:

1. Develop architecture, concepts and requirements for intent-driven system generators.

2. Develop and deliver automated software required for high-level synthesis, including reference design generators, intent-driven synthesis, high-level system design entry, and automated COTS part database creation.

3. Identify parts library modeling requirements based on the needs of the system generator and circuit optimization tools. Create methods for extracting model information from elements added to the Open Parts database.

4. Create a vast library of COTS parts modeled using extended IC formats such as GDSII, LEF, LIBERTY, IP-XACT. At a minimum, the library should include all parts needed design the Phase 1 benchmarks, as identified in Table 3. Proposers are encouraged to create fully automated data mining and model technology to enable automated model creation for close to all 5M+ open parts in circulation.

5. Utilize existing commercial PCB layout tools to create physical layouts of the structured netlists created by the IDEA TA-2 generators in preparation for manufacturing early in Phase 2.

Phase 2: Optimization and System Demonstration [Option – 24 months] In Phase 2, performers are expected to:

1. Manufacture boards designed in Phase 1 using the IDEA system synthesis platform and traditional physical layout tools.

2. Integrate the front-end system generator software created in Phase 1 of TA-2 with the physical layout generator created by TA-1 and produce a fully automated end-to-end electrical system generator.

3. Manufacture and deliver boards designed with the fully automated end-to-end electrical system generator.

4. Actively optimize software and documentation to enable adoption by a large number of new users to ensure successful software transition at the end of the program. Models library developers should continue adding elements to the Open Parts Database, and demonstrate successful use of the model library within the design flow.

Table 3. TA-2 metrics by Phase.

Technical Area Metrics Phase 1 Phase 2

SoC Benchmark SoC with 10 IPs SoC with 100 IPs

PCB Benchmark BeagleBone Black1 Open Compute Board2

SiP Benchmark Establish pathway to SiP generation

Demonstrated fully automated layout of

SiPs with >100 chiplets and >100,000 nets

Benchmark PPAIDEA/PPATraditional

(3) 0.5 1

Automation 100%

Turn around time 24 hours

TA–2:

Intent Driven System

Synthesis

Deliverable Software, license4, documentation 1This metric is a measurement of functional equivalence to a BeagleBone Black circuit card.

2This metric is a measurement of functional equivalence to an Open Compute Server.

3Relative Power, Performance, Area as compared to benchmark design completed by a small physical design team using off-the-shelf tools current to 2017 commercial EDA ideology. Higher numbers indicated higher quality with “1” being the current status.

4Delivered with a minimum of government purpose rights; open source licenses are preferred.

A selectable proposal for one or more subtasks of the IDEA TA-2 framework must include the following:

A description clearly stating whether the proposed software module supports a step in one of the three sub-tasks identified in TA-2

A description of the unique technical merits and value provided by the technology to meet the goals of IDEA TA-2 as described above. Proposers may use prior work to argue the technical merits of their approach.

A description of each proposed software module and its function

A description of how proprietary trained “knowledge models” will be separated from the main system generator and how communication with said model is handled.

A list of constraints for the software module, identifying the source of the constraints (whether from other software module or initial user input)

A full description of required design inputs, where applicable A full description of design outputs, where applicable A discussion of the plan to achieve autonomous functionality for the software module in the following regards:

o Autonomous operation – given inputs and constraints, produce output without human intervention o Autonomous handoff – condition outputs such that they can be used by other modules without human intervention A description of the proposer’s anticipated software release schedule:

o Public releases of software are required at the end of each phase o At a minimum, controlled releases should occur on an industry-leading collaborative development platform prior to each scheduled integration exercise.

Additional releases to facilitate integration are strongly encouraged

A description of appropriate mid-phase technical metrics applicable to the evaluation of the proposed software modules

5. Schedule and Milestones

The IDEA program schedule comprises a 24-month base period (Phase 1) followed by a 24-month option period (Phase 2), for a total of 48 months, subject to availability of funds and technical progress achieved. Due to the likelihood that performers will be developing individual modules of a software platform, proposers will be required to establish intermediate goals and milestones that support their strategies.

Performers will be assessed throughout the program based on their individual technical progress as well as the performance of the full IDEA software platform against the program metrics.

USG/FFRDC testing and evaluation of the software design platform developed in IDEA will be conducted throughout the course of the program, and performers are expected to address feedback from evaluations. Approval of the next funding increment will require satisfactory progress against the performer’s metrics and a clear plan to achieving the program requirements and platform metrics. A program schedule with critical milestones is provided in Figure 6.

Phase 1 Milestones:

TA-1: Creation of a “no human in the loop” unified layout generator, and physical design of the benchmark circuits meeting the program metrics. Alpha, beta and public releases of the software platform and associated software modules. Complete physical design of an SoC and deliver a GDSII database ready for manufacturing at the end of Phase 1 (with the expectation of tapeout early in Phase 2).

TA-2: Development of a COTS open parts library and an intent-based system generator supporting SoCs, SiPs, and PCBs. Layout of a PCB and SiP using the TA-2 high-level synthesis tools coupled with traditional back-end physical design tools.

Phase 2 Milestones:

TA-1: Tapeout SoC in 14nm CMOS at beginning of Phase 2, and evaluate fabricated SoCs upon return. Optimize the software modules based on hardware results to feed into a 2.0 software release that is used to tapeout a second SoC. Integration of new training sets to upgrade algorithms in the final year, with a final version 3.0 release at the end of the program. The final year of the program is also expected to focus on increasing the number of users and reducing the barriers to entry for new software developers to ensure a stable, widespread user community after the program ends.

TA-2: Optimization of the first software release based on characterization of hardware fabricated at the beginning of Phase 2. Fabrication of a second round of hardware using the version 2.0 software and the IDEA layout tool, for completed automated physical design of SiPs and PCBs.

Figure 6. An illustration of the IDEA program schedule highlighting critical program events and milestones.

6. Program Deliverables

The IDEA program deliverables are summarized in Table 4.

Table 4. Summary of IDEA program deliverables by phase and technical area.

Phase IDEA TA-1 IDEA TA-2

Layout generator software and any required licenses

Trained models Documentation GDSII database

System synthesis software and any required licenses

Trained Models Documentation Library of open COTS components

Reports as defined below Reports as defined below

Layout generator software and any…