JA_18-41_Redacted.pdf

DMEA #18-41

Defense Microelectronics Activity 4234 54th Street, McClellan, CA 95652

SOW 18-8F8

Sole Source Justification

1. Agency and Contracting Activity:

Office of Secretary Of Defense, Defense Microelectronics Activity (DMEA).

2. Nature/Description of Action:

Acquisition of Cadence System-on-Chip (SoC) and Application Specific Integrated Circuit (ASIC) Verification Platform, Electronic Design Automation (EDA) Software, and Process Development Kit (PDK) Development. The value of this procurement is estimated to be

3. Description of Supplies/Services:

The Palladium Z1 GXL platform - is a rack-based, ASIC verification platform. It is suited for hardware and software co-verification and system realization of register-transfer level (RTL) abstraction.

The EDA software licenses - are utilized for custom integrated circuit design.

Process Development Kit (PDK) Development -Cadence will migrate and update/enhance a PDK that exists in an older version of the Cadence platform. The PDK provides DMEA with the capability to design integrated circuits for the corresponding process.

4. Authority Cited:

FAR 13.501(a)(1)(ii) Simplified Procedures for Certain Commercial Items; 41 U.S.C. 1901.

5. Reason for Authority Cited:

The Palladium Z1 GXL platform - only the SoC and ASIC Design Verification Capability manufactured by Cadence can satisfy because the platform must be a Cadence product to support a Cadence environment that DMEA is already using. Only the Palladium is a processor-based architecture, while other emulators are FPGA-based architectures. The processor-based architecture provides benefits such as being able to debug the design in real-time and having access to any net, which is not possible in a FPGA-based architecture.

perform debug.

EDA Software Licenses DMEA process development kits were developed for the specified EDA software licenses to be acquired. DMEA has purchased these tools in the past. The Cadence software licenses to be acquired serve as computer aided design (CAD) tools to design

FPGA based architecture, the way the FPGA is partitioned at routed determines the speed which usually never is X MHz.

2) ASIC or digital gate count of a design maps directly to the processor based architecture.

100k RTL gates = 100k Palladium gates. Again, in an FPGA, it depends on how the design is partitioned and routed. In an FPGA, it is never 1:1.

With the processor based architecture, the debug capability is more expansive. In FPGA based s which makes it harder The Palladium platform enables transition among simulation, simulation acceleration, and emulation environments at runtime without re-compilation.

Other vendors can provide the general capability of emulation, but performance, form factor, and cost vary.

The contract specialist reviewed the Department of Defense Enterprise Software Initiative (DoD ESI) website to seek information on blanket purchase agreements (BPA) for Cadence software.

No DoD ESI BPA for Cadence software was found.

Further market research was conducted to identify potential sources. The results of this research are documented in the table below:

Contractor Capability Result EMA Design Automation Authorized distributor of Cadence software.

Sells Cadence software only for designing PCBs immixGroup GSA software wholesaler No response CounterTrade Products NASA SEWP contract holder Cannot provide Virtuoso

Design software and is not an Cadence authorized reseller

Intelligent Decisions NASA SEWP contract holder Cannot provide Virtuoso Design software and is not an Cadence authorized reseller

Cadence Design Systems Manufacturer of Virtuoso Design Implementation software

Cadence Virtuoso Digital Implementation software cannot be obtained from a third party.

Cadence owns the software/platform, and they create PDK components in their own software/platform. Due to the proprietary data rights, other EDA vendors such as Mentor Graphics or Silvaco would not have the capability .

9. Other Facts:

DoD Trusted Suppliers, including Harris Semiconductor and IBM, use the Cadence Design Suite to develop ASIC PDKs.

Chief of Contracting/Competition Advocate