DARPA-BAA-16-62-Amendment-02.pdf

DARPA-BAA-16-62

Broad Agency Announcement Common Heterogeneous Integration and IP Reuse Strategies

(CHIPS)

Microsystems Technology Office

DARPA-BAA-16-62

September 29, 2016

(Amendment No. 02: As amended through December 21, 2016)

Table of Contents

PART I: OVERVIEW INFORMATION

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description A. Background B. Program Description C. Program Structure D. Technical Areas

1. Technical Area 1 (TA1): Modular Digital Systems

2. Technical Area 2 (TA2): Modular Analog Systems

3. Technical Area 3 (TA3): CHIPS Supporting Technologies

4. Technologies NOT Included

E. Schedule/Milestones F. Deliverables G. Government Furnished Equipment/Property/Information

II. Award Information III. Eligibility Information

A. Eligible Applicants B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and

Organizational Conflicts of Interest C. Cost Sharing/Matching D. Other Eligibility Criteria

1. Collaborative Efforts E. Associate Contractor Agreement (ACA) Clause

IV. Application and Submission Information A. Address to Request Application Package B. Content and Form of Application Submission

1. Abstract Format

2. Full Proposal Format

3. Proprietary Information

4. Security Information

5. Submission Information

a. Abstract Submission Information

b. Proposal Submission Information

6. Submission Dates and Times

7. Funding Restrictions

8. Other Submission Requirements

V. Application Review Information A. Evaluation Criteria B. Review and Selection Process

VI. Award Administration Information A. Selection Notices

1. Abstracts

2. Proposals

B. Administrative and National Policy Requirements

1. Meeting and Travel Requirements

2. Human Subjects Research

3. Animal Use

4. Export Control

5. Subcontracting

6. Electronic and Information Technology

7. Employment Eligibility Verification

8. Reserved

9. System for Award Management (SAM) and Universal Identifier Requirements

10. Reporting Executive Compensation and First-Tier Subcontract Awards

11. Updates of Information Regarding Responsibility Matters

12. Representations by Corporations Regarding an Unpaid Delinquent Tax Liability or a Felony Conviction under any Federal Law

13. Cost Accounting Standards (CAS) Notices and Certification

14. Controlled Unclassified Information (CUI) on Non-DoD Information Systems

15. Safeguarding of Covered Defense Information and Cyber Incident Reporting

16. Prohibition on Contracting with Entities that Require Certain Internal

Confidentiality Agreements C. Reporting D. Electronic Systems

1. Representations and Certifications

2. Wide Area Work Flow (WAWF)

3. i-Edison

VII. Agency Contacts VIII. Other Information

A. Intellectual Property Procurement Contract Proposers

1. Noncommercial Items (Technical Data and Computer Software)

2. Commercial Items (Technical Data and Computer Software)

B. Non-Procurement Contract Proposers – Noncommercial and Commercial Items (Technical Data and Computer Software)

C. All Proposers – Patents D. All Proposers – Intellectual Property Representations E. Other Transactions (OTs):

ATTACHMENT 1: Proposer Checklist ATTACHMENT 2: Proposal Summary Slide Template

PART I: OVERVIEW INFORMATION

Federal Agency Name – Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO) Funding Opportunity Title – Common Heterogeneous Integration and IP Reuse

Strategies (CHIPS) Announcement Type – Initial Announcement Funding Opportunity Number – DARPA-BAA-16-62 Catalog of Federal Domestic Assistance Numbers (CFDA) – 12.910 Research and

Technology Development Dates (All times listed herein are Eastern Time) o Posting Date: September 29, 2016 o Proposers Day: September 21, 2016 o Abstract Due Date: 1:00 PM on October 28, 2016 o FAQ Submission Deadline: 1:00 PM on December 30, 2016 o Proposal Due Date: 1:00 PM on January 13, 2017 o Estimated period of performance start: 120 calendar days after proposal submission.

Concise description of the funding opportunity: The Common Heterogeneous

Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program will develop the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of DoD and commercial designs and technology.

Anticipated Funding Available for Award: DARPA anticipates a funding level of approximately $70M for the CHIPS program.

Anticipated individual awards – Multiple awards in each Technical Area are anticipated.

Anticipated funding type - 6.2 and/or 6.3 Types of instruments that may be awarded – Procurement contract, grant, cooperative agreement or other transaction.

Agency contact o Dr. Daniel Green, Program Manager BAA Coordinator: DARPA-BAA-16-62@darpa.mil

DARPA/MTO

ATTN: DARPA-BAA-16-62

675 North Randolph Street Arlington, VA 22203-2114

PROPOSERS ARE CAUTIONED THAT EVALUATION RATINGS MAY BE LOWERED AND/OR PROPOSALS

REJECTED IF PROPOSAL PREPARATION (PROPOSAL FORMAT, CONTENT, ETC.) AND/OR SUBMITTAL

INSTRUCTIONS ARE NOT FOLLOWED.

THOSE INTENDING TO SUBMIT A PROPOSAL FOR AN ASSISTANCE INSTRUMENT (GRANT OR

COOPERATIVE AGREEMENT) ARE STRONGLY ENCOURAGED TO READ THE INSTRUCTIONS PROVIDED

AT SECTION IV(B)(4) REGARDING THE TIME REQUIRED TO RECEIVE VALIDATION OF SUBMISSIONS

MADE THROUGH GRANTS.GOV. PROPOSALS THAT ARE VALIDATED AFTER THE PROPOSAL DUE

DATE/TIME WILL BE CONSIDERED LATE AND, AS SUCH, WILL NOT BE REVIEWED.

mailto:name@darpa.mil

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description

The Defense Advanced Research Projects Agency (DARPA) often selects its research efforts through the Broad Agency Announcement (BAA) process. This BAA is being issued, and any resultant selection will be made, using the procedures under Federal Acquisition Regulation (FAR) 6.102(d)(2) and 35.016, and 2 C.F.R. § 200, as applicable. Any negotiations and/or awards will use procedures under FAR 15.4, Contract Pricing, and 2 C.F.R § 200, as applicable.

Proposals received as a result of this BAA shall be evaluated in accordance with evaluation criteria specified herein through a scientific review process.

DARPA BAAs are posted on the Federal Business Opportunities (FedBizOpps) website, http://www.fbo.gov/, and, as applicable, the Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA.

The Microsystems Technology Office at DARPA seeks innovative proposals in the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of Department of Defense (DoD) and commercial designs and technology.

Proposed research should investigate innovative approaches that enable revolutionary advances in science, devices, or systems. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice.

A. Background

The explosion of growth in mobile and telecommunication markets has pushed the semiconductor industry towards integration of digital, analog and mixed-signal blocks into system-on-chip (SoC) solutions. Advanced silicon (Si) complementary metal oxide semiconductor (CMOS) technology has enabled this integration, but has also led to a rise in costs associated with design and processing. Intellectual Property (IP) reuse has emerged as a tool to help lower design costs, though it is primarily used in the digital domain for high volume designs. The complexity and typical custom nature of advanced analog circuit design makes it risky to reuse analog IP blocks and for both digital and analog designs, low volume design leads to high IC development costs. These high costs disproportionately affect low volume consumers such as the DoD. To enhance overall system flexibility and reduce design time, reusable design challenges in the digital and analog domains must be addressed.

A candidate solution to address the challenges of low volume design is to extend the strategy of IP reuse at the hardware level. Chip level integration has now emerged as a primary strategy to increase integration density in the Si CMOS community, as the advancement of traditional transistor scaling has slowed. Both 2.5D and 3D integration flows currently exist for specific CMOS technologies, such as stacked memory, but these flows are typically proprietary and applicable to a limited set of process technologies. The lack of a standardized integration interface limits the ability to utilize integration for IP reuse at the chip level. This situation also slows realization of new circuit designs and adoption of new process technologies.

http://www.fbo.gov/ http://www.grants.gov/

Beyond Si CMOS electronics, and particularly in the analog domain, long-term research in more exotic platforms, such as GaAs, InP, SiGe, and GaN have yielded distinct technological advantages. However, in many of these cases, it took over a decade to bring these discoveries from the lab to demonstrable products in the field. At the same time, the diffusion of technologies around the world has accelerated. Continued presence at the technological forefront will require a faster advanced technologies adoption process and a shorter ramp for integrating new device technologies into the design toolbox.

B. Program Description

The goal of the CHIPS program is to establish and demonstrate a modular design and fabrication flow for electronic systems while addressing the rising cost, lead-time, and complexity of IC design. The central idea is that a system can be subdivided into functional circuit blocks or chiplets that are reusable IP blocks, where an IP block refers to a pre-designed functional circuit block realized in physical form.1 Complete electronic systems can then be created through integration of chiplets on an interposer, rather than through the design and fabrication of circuits in a monolithic flow. This modular design flow is anticipated to encompass rapid assembly and reconfiguration of various IP blocks through standard layouts and interfaces2 seamlessly linked to other chiplets. This common framework is expected to expand access to a large catalog of commercial off-the-shelf (COTS)/Government off-the-shelf (GOTS) IP blocks, allow reuse of existing IP blocks, and speed heterogeneous integration of blocks in other technologies and nodes. The overall CHIPS program is envisioned as the establishment, demonstration, and iteration of modular design flows enabled by interface standardization.

The application of a CHIPS modular design flow is expected to lead to a 70% reduction in design cost and turn-around time. To realize these benefits, CHIPS will explore the design tools, integration methodologies, and interface standards necessary to rapidly integrate chiplets. By the end of the program, teams will have demonstrated not only functional modules built using

1 Examples of IP blocks include, but are not limited to, timing circuits, filters, waveform generators, embedded processors, data converters, amplifiers, and memory.

2 There are many interface standards in place (e.g., LVDS, AMBA/AXI, AIB/UIB, JESD204B, JESD229 (Wide I/O), JESD235 (HBM)), but these have not been instantiated in hard IP for heterogeneous integration.

chiplets but also a set of standard interfaces that can be used in future designs that leverage reusable chiplets.

The CHIPS program is expected to demonstrate that a modular design strategy using chiplets can enable the development of high-performance electronic systems quickly and at low cost. The envisioned capabilities at the end of the program are: 1) modular design tools, 2) a set of interface standards that would enable IP reuse in future electronic designs, and 3) a verified collection of IP blocks that were demonstrated and are available for future programs. The program explicitly targets enhanced leverage of commercial technologies as a significant piece toward achieving these goals and thus enhanced relationships and strategies for interaction with the commercial sector beyond the Defense industrial base are also desired.

C. Program Structure

The CHIPS goal of establishing a modular design flow and pre-fabricated chiplet collection leads to a program centered on the development and demonstration of complete, integrated circuits with full system capabilities, the performance equivalent of a conventional electronics module, where these circuits will be composed of integrated chiplets. These modular design demonstrations are the heart of the CHIPS program to provide both the driver for the design flow and the test vehicle for its effectiveness. However, supporting technologies that enable these modular designs will be entertained and are expected to be a significant part of the effort as described below. Finally, while the philosophy is similar for both digital and analog modular circuits, the technical details drive to different requirements for standardized interfaces. For this reason, CHIPS will contain two technical areas (TAs) that target digital and analog circuits in independent, parallel paths.

There are no specific application areas required for CHIPS since the focus of this program is on enabling modular design rather than solving a specific design challenge. DARPA expects that performers will leverage existing designs that would benefit from translation to a modular framework in order to enable reuse of captive IP, to include commercial IP, or to allow faster redesign and update cycles. Designs that demonstrate these benefits of IP reuse and feature the opportunity for rapid design evolution in DoD relevant electronic systems are sought for CHIPS.

A key feature of the CHIPS program is the establishment of standardized interfaces to promote the reusability and interchangeability of modular circuit functional blocks or chiplets. Beyond the technical areas and individual performer roles, the goal of the program is to establish a working community that will converge on a limited number of interface standards that are broadly useful. To that end, the program will feature regular technical interchange meetings anticipated to occur as monthly teleconferences and quarterly meetings through Phase 1 to facilitate consensus building, develop common practices and standards of engagement, as well

CHIPS

as, most importantly, define common interfaces. Performers will need to adopt a common interface to proceed beyond the interface critical design review at eight months into the program.

The goal is to ensure that the program converges on and leverages a small set of interfaces early.

The CHIPS schedule is described more fully below.

D. Technical Areas

The CHIPS program consists of one technical area (TA1) focused on modular digital designs and a second technical area (TA2) focused on modular analog designs. Each TA will progress through phases that will establish common interfaces, demonstrate modular designs utilizing these interfaces, and rapid iteration of designs to exercise the design flow. The technical areas are summarized in the table below and described more fully in the following text. Additionally, any CHIPS supporting technology should align to one or both of these technical areas but is captured separately as a third technical area (TA3).

Table 1: Technical Area Summary

PHASE 1 PHASE 2 PHASE 3

Interface and IP Block Demo Module Demo with IP Blocks Rapid Module Upgrade

TA1 Modular Digital Systems Digital Interface and IP Blocks Create a modular design derived from existing digital designs leveraging an established interface standard.

Establish common interface standards at a critical design review (CDR) at 8-month mark.

Demonstrate functional IP blocks that utilize the established interface standards.

Module Demo with IP Blocks Demonstrate functional digital module using Phase 1 blocks.

Perform analysis to compare cost and development time of the CHIPS module versus a monolithic implementation.

Present design for a prototype module for meeting the Phase 3 metrics at a preliminary design review (PDR).

Rapid Module Upgrade Demonstrate a rapid upgrade prototype with the modular CHIPS design flow, verifying unique modules can be rapidly assembled by reusing IP blocks from various sources and technologies.

Perform an analysis to compare cost and development time of the CHIPS module versus a monolithic implementation.

TA2 Modular Analog Systems Analog Interface and IP Blocks Design modular analog building blocks that disaggregate a pre-existing analog design and demonstrate a common analog interface standard.

Review design and interface at the 8-month mark, and demonstrate interconnect performance.

Module Demo with IP Blocks Integrate analog building blocks into “Pseudolithic” microwave Integrated Circuit (PLIC).

Evaluate metrics benchmarked to state of the art (SoA) performance, unit cost, non-recurring engineering (NRE) costs, and turnaround time.

Develop business model for modular analog ecosystem.

Rapid Module Upgrade Demonstrate rapid assembly of new

PLICs using modular designs, common interfaces, and analog blocks demonstrated in Phase 2.

Evaluate metrics benchmarked to SoA performance, cost, NRE, and turnaround time.

Perform analysis to compare cost and development time of the CHIPS module versus a monolithic MMIC.

1. Technical Area 1 (TA1): Modular Digital Systems

In TA1, performers should propose modular designs around digital IP blocks that leverage pre-existing proprietary and commercial designs. The central technical challenge for a digital CHIPS ecosystem will be the definition and acceptance of a limited set of common interface standards that support the data movement intensive operations and control signaling required for modular digital processing with near monolithic performance. Proposers should address how their designs will leverage these interfaces, impose requirements on the interfaces and how they plan to engage in the definition of the interface(s). It is expected that proposers will leverage emerging capability in 2.5D integration that enables high density interconnects with lower latency and loss than is available via conventional packaging technology and on par with monolithic interconnect bus standards. The challenge of defining a limited number of CHIPS interfaces will require balancing competing requirements for low energy, low latency, data flow, control flow, and scalability. Mixed-signal designs such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) where the digital interface is being addressed can be included in TA1.

Phase 1: Interface and IP Block Demonstration (Base – 18 months) In order to quickly arrive at a limited set of interface standards, Phase 1 teams will initiate a modular design effort derived from existing, complete designs. Proposers should detail how they intend to create a modular design and contribute to both the interface development based on design considerations and what IP is expected to be available to the CHIPS community as a result of the effort. The historical design effort data for the existing design should also be compared as a benchmark to the cost and time of the proposed modular design.

A critical interface design review (CDR) will be held at the 8-month mark to establish common interface standards to be used in the TA1 designs. The performer set will be refined by DARPA at this 8-month milestone to assure that all performers are adopting common interfaces.

Proposers should then describe how their design will then test the standard interfaces for a limited case of coupling of IP blocks, and complete a preliminary design review (PDR) for an initial prototype module.

Phase 2: Module Demonstrations with IP Blocks (Option – 18 months) During Phase 2, proposers should use the demonstrated functional interface and complete design of all chiplets required for a fully functional module. The proposal should document how chiplets will then be fabricated, the complete functioning module will be assembled and the plan to evaluate metrics for the amount and nature of the IP integrated into the module, as well as non-recurring engineering (NRE) expense and turnaround time. Proposers should include a benchmark comparison to state-of-the-art performance, cost, and size, weight and power (SWAP). At the end of Phase 2, teams should also complete a preliminary design review (PDR) with fully documented reference design flows for a prototype module meeting the Phase 3 metrics. Additionally, performers are asked to provide a business model for how the DoD community will access CHIPS technology.

Phase 3: Rapid Module Upgrade (Option – 12 months) Phase 3 should be used by proposers to demonstrate and characterize a rapid upgrade prototype that leverages the modular design flow developed in the program. The goal of this phase is to show that unique modules can be rapidly assembled by reusing IP blocks from various sources and of different technologies. A cost analysis to compare cost and development time of the CHIPS module versus a monolithic instantiation is also sought.

2. Technical Area 2 (TA2): Modular Analog Systems

In TA2, performers should propose high performance analog circuits to be realized from modular building blocks by developing analog device and circuit assembly techniques. A useful concept here is that of a “pseudolithic” microwave integrated circuit (PLIC), which approaches the performance of a monolithic microwave integrated circuit (MMIC) through integration of chiplets rather than a monolithic design process. The interfaces, both physical and electronic, should enable this near-monolithic performance. The central challenge to realizing a modular analog process is determining the scale of useful modular cells ranging from the transistor unit cell level to functional analog block, e.g., oscillator, mixer, or amplifier gain stage. The level of modularity is tightly coupled to the performance of the interconnect points, with higher performance interconnects enabling more granular building blocks. The interconnect performance must also be balanced by the requirement for a standard interface needed to ensure compatibility between unit cells in diverse technologies. Proposers should address what level of modularity their designs target and how the community will access and benefit from the ecosystem of these analog building blocks.

Phase 1: Interface and Demonstration of Modular Analog Building Blocks (Base – 18 months) In Phase 1, teams should design modular analog building blocks that appropriately disaggregate a pre-existing analog design and demonstrate a common analog interface standard. The design and choice of interface will be reviewed at the 8-month mark, with a demonstration of the interconnect performance by the end of Phase 1.

Phase 2: PLIC Demonstration with Modular Unit Cells (Option – 18 months) Analog building blocks designed and demonstrated in Phase 1 should then be integrated into a functional “pseudolithic” microwave integrated circuit (PLIC) in Phase 2, with metrics for NRE and turnaround time reduction, and benchmarked to state-of-the-art performance, cost, and SWAP. Additionally, performers are asked to provide a business model for how the DoD community will access CHIPS technology in a modular analog ecosystem.

Phase 3: Rapid Module Upgrade (Option – 12 months) In Phase 3, modular designs, common interfaces, and fabrication of analog unit cells demonstrated in Phase 2 should be leveraged to show rapid assembly of new PLIC modules. A cost analysis should be performed at the end of the phase to compare cost and development time of the CHIPS module versus a monolithic instantiation.

Table 2: Program Metrics (TA1 and TA2)

Notes:

1. Public IP is defined as IP blocks available through commercial vendors or shared among performers.

2. Reuse is defined as existing or previously designed IP that is re-implemented into the current system.

Prefabricated IP is defined as IP blocks already physically instantiated.

3. Valid sources of IP must be those that are outside of the performer team.

4. Various Silicon process nodes, RF passives, or compound semiconductor devices.

5. The non-recurring engineering (NRE) cost and turnaround time will be compared against a benchmark design.

6. Minimum bus/lane data rate per interface instantiation, and should be capable of scaling to higher data rates.

7. Performance relating to transferring data between chiplets compared against a benchmark design.

Along with the specific performance metrics in Table 2, proposals will be evaluated based on the viability of the chiplets of public IP for reuse. Accordingly, chiplets with broad applicability and a clear mechanism for availability are desired.

Note that the interface metrics are intended to guide proposers to use the best demonstrated technology, but does not seek to drive extreme performance solutions. Ideally, CHIPS solutions will balance high performance interfaces with standards that are maximally reusable and as simple as possible. The interface standards in the CHIPS program do not need to include standards for physical interfaces (e.g., standard chiplet interconnect footprint). However, any physical commonality that adds to the ease of reuse without limiting applicability could be seen

CHIPS Program Metrics Metric Phase 1 Phase 2 Phase 3

Design level IP reuse (1) > 50% public IP blocks > 50% public IP blocks > 50% public IP blocks

Modular design (2) > 80% reused, > 50% prefabricated IP

Access to IP (3) > 2 sources of IP > 2 sources of IP > 3 sources of IP Heterogeneous integration

(4) > 2 technologies > 2 technologies > 3 technologies

NRE reduction (5) > 50% >70% Turnaround time reduction

(5) > 50% >70%

Performance benchmarks (performer defined) >95% benchmark >100% benchmark

Digital interfaces Data rate (scalable) (6) 10 Gbps 10 Gbps 10 Gbps Energy efficiency (7) < 1 pJ/bit < 1 pJ/bit < 1 pJ/bit Latency (7) ≤ 5 nsec ≤ 5 nsec ≤ 5 nsec Bandwidth density > 1000 Gbps/mm > 1000 Gbps/mm > 1000 Gbps/mm

Analog interfaces Insertion loss (across full bandwidth) < 1 dB < 1 dB < 1 dB

Bandwidth ≥ 50 GHz ≥ 50 GHz ≥ 50 GHz Power handling ≥ 20 dBm ≥ 20 dBm ≥ 20 dBm as a benefit. Design teams should also be prepared for a possible update to the interface standard at the end of Phase 1, based on results from the interface demonstration at the 18-month point that follows the interface selection at the 8-month point.

Proposers are invited to propose complete solutions to TA1 or TA2 in separate proposals.

Proposers may also propose to both TA1 and TA2 in a single proposal if there is a clear rationale. Combined TA1 and TA2 proposals should clearly delineate which tasks would be required if only a TA1 or TA2 solution is desired. Alternately, proposers may target Technical Area 3 (TA3) below. (See the Table 3 for a summary of Proposal Options by TA.) Proposers may submit multiple proposals.

Table 3: Proposal Options by Technical Area

Proposal Options Option 1 Option 2 Option 3 Option 4

TA1 (Digital) X X TA2 (Analog) X X TA3 (Supporting) X

3. Technical Area 3 (TA3): CHIPS Supporting Technologies

For both Technical Areas 1 and 2, the modular design demonstration is the center of the CHIPS program and will provide both the driver for the design flow and the test vehicle for its effectiveness. This design will require performers to develop and implement modular designs derived from existing designs for systems of interest to the DoD. However, it is also expected that supporting technologies such as new design tools, methods to enable assembly of chiplets, or alternate sources of specific IP blocks will be desired to fully realize the CHIPS ecosystem and maximize the performance of the modular designs. Additionally, these supporting technologies will be most impactful if available across the CHIPS community and developed in conjunction with the CHIPS interface standards that meet the range of requirements for the program.

Therefore, DARPA also encourages proposals for CHIPS supporting technologies that address a subset of the challenges of CHIPS. Examples of supporting technologies include electronic design automation (EDA) tools for heterogeneous integration and modular design flows, processes and technologies for physical integration of chiplets to address challenges such as pitch and small device testing and handling, and IP blocks of designs elements that do not comprise a complete system but are broadly useful to the community. A listing of such candidate IP blocks that could be broadly useful can be found below in Table 4.

Table 4: Sample IP Blocks

Sample Digital IP Blocks Processor

Image Signal Processor Audio Signal Processor DSP Compression GPU Machine Learning CPU

Interface / Networking SerDes USB PCIe

Memory Controller DRAM Flash SRAM

Sample RF, Analog, and Mixed Signal IP Blocks Transistor Unit Cell Passives Amplifiers LNA Mixer

PLL DAC ADC

Filters Envelope Tracker PMIC

For supporting technologies, proposers should clearly establish which technical area or areas (i.e.

TA1 and/or TA2) are aligned as well as propose metrics relevant for the development consistent with the technical area metrics in the table above. Additionally, the utility of supporting technology to the CHIPS ecosystem will need to be demonstrated early in the process. The critical design review at the 8-month mark will be especially important for supporting technologies to gauge community adoption. Adoption or planned adoption will be gauged among CHIPS participants and/or DoD development partners.

Performers in all performer roles will be expected to participate in the regular technical interchange meetings so that interface standards, best practices, and design requirements can easily flow among groups.

4. Technologies NOT Included

The CHIPS program is not intended to fund development of new device technology. The focus is on interfaces, modular design, and IP blocks, so new device types (developed elsewhere) can be part of the program but only as they relate to defining or demonstrating the focus areas of CHIPS. For example, development of novel memory structures, new device materials, or novel security components are not of interest to the CHIPS program. Development of an interface that allows for inclusion of novel device technologies would be a candidate topic for funding under CHIPS. Similarly, the CHIPS program will not fund wholly new IP and circuit designs, although such IP and designs can be included in the program if the development is funded outside the program, with the CHIPS-funded effort focused on the interface and integration. To the maximum extent possible, reuse of existing designs is preferred with significant design work expected in translating existing designs into the modular CHIPS framework.

Additionally, it is expected that software development may be needed to enable some CHIPS approaches (e.g., for programmability). However, this is not the focus of the CHIPS program, so CHIPS will fund such development only as needed to demonstrate functionality of interface standards, IP blocks, and modular design demonstrations. A complete general solution to software challenges is beyond the scope of the CHIPS program.

E. Schedule/Milestones

The program will use a single BAA to solicit research proposals that achieve the program goals.

Due to the possibility of multiple paths for achieving the program goals, proposers will be required to establish intermediate goals and milestones that support their strategies.

The CHIPS program is expected to span the course of four years and will be divided into three separate phases. In Phase 1, performers will demonstrate the necessary tools and integration strategy to enable chiplet-based IP reuse. By the end of Phase 1, teams are expected to demonstrate functional chiplets and flexible integration platforms. Chiplets should leverage standard interfaces so that they can be used by other teams in the program. In Phase 2 performers will need to show that functional modules incorporating multiple device technologies from multiple IP sources (e.g., commercial, internal, or among performers). The goal of Phase 3 is to exercise the CHIPS ecosystem by demonstrating rapid module reconfigurability.

All performers will be assessed throughout the program based on their technical progress and in accordance with their proposed schedule of intermediate milestones. Independent testing and validation of IP blocks and device performance metrics will also be performed over the course of the program. Approval of the next funding increment will require satisfactory progress against the performer’s current metrics and clear plan to achieving the program requirements and system metrics. A refinement of the performer set is expected to occur during Phase 1 at the 8-month interface milestone (M1), at the end of Phase 1, and at the end of Phase 2.

Table 4: CHIPS Program Technical Milestones

Technical Milestones M1: Critical Design Review (CDR) of common interface standards (8 months) M2: Demonstrate standard interfaces (18 months) M3: Preliminary Design Review (PDR) for full module (18 months) M4: Demonstrate functional module (36 months) M5: Preliminary Design Review (PDR) for upgrade prototype (36 months) M6: Demonstrate rapid upgrade prototype (48 months)

Table 5: CHIPS Program Timeline

F. Deliverables

The performer deliverables will depend on the scope of the work. As mentioned above, DARPA expects some proposals to cover the full design effort (i.e. TA1 and TA2), and the deliverables for those performers are listed below. Performers who are addressing only partial solutions will have a different specific set of deliverables that should be consistent with enabling independent verification and validation of components by third parties.

Phase 1 Deliverables:

Definition of interface standards to be complete at 8 months (CDR) Preliminary Module Design (including interface standards) Functioning, chipletized IP blocks or analog building blocks with test report Report documenting the design approach

Phase 2 Deliverables:

Complete modular systems of chipletized IP blocks with characterization data Fully documented reference CAD flow Cost analysis documenting time and cost savings Report documenting the approach

Phase 3 Deliverables:

Complete iterated, modular systems of chipletized IP blocks with characterization data Updated documented reference CAD flow Cost analysis of approach compared to reference design Report documenting the approach

G. Government Furnished Equipment/Property/Information

No IP is currently provided for CHIPS performers, however the Government will provide public notice if specific IP blocks become available. The government will provide access to wafer processing runs in advanced Silicon CMOS technology via the capabilities established in DARPA/MTO’s CRAFT program. The details and associated costs, which should be included in any CHIPS proposal, can be obtained upon request at:

https://www.mosis.com/db/pubf/cact?page_type=doc_access_req

II. Award Information

Multiple awards are anticipated. The amount of resources made available under this BAA will depend on the quality of the proposals received and the availability of funds.

The Government reserves the right to select for negotiation all, some, one, or none of the proposals received in response to this solicitation, and to make awards without discussions with proposers. The Government also reserves the right to conduct discussions if it is later determined to be necessary. If warranted, portions of resulting awards may be segregated into pre-priced options. Additionally, DARPA reserves the right to accept proposals in their entirety or to select only portions of proposals for award. In the event that DARPA desires to award only portions of a proposal, negotiations may be opened with that proposer. The Government reserves the right to fund proposals in phases with options for continued work at the end of one or more of the phases, as applicable.

Awards under this BAA will be made to proposers on the basis of the evaluation criteria listed below (see section labeled “Application Review Information,” Sec. V.), and program balance to provide overall value to the Government. The Government reserves the right to request any additional, necessary documentation once it makes the award instrument determination. Such additional information may include but is not limited to Representations and Certifications (see Section VI.D.1., “Representations and Certifications”). The Government reserves the right to remove proposers from award consideration should the parties fail to reach agreement on award terms, conditions and cost/price within a reasonable time or the proposer fails to timely provide requested additional information. Proposals identified for negotiation may result in a procurement contract, grant, cooperative agreement, or other transaction, depending upon the nature of the work proposed, the required degree of interaction between parties, whether or not the research is classified as Fundamental Research, and other factors.

In all cases, the Government contracting officer shall have sole discretion to select award instrument type and to negotiate all instrument terms and conditions with selectees. Proposers are advised that regardless of the instrument type proposed, DARPA personnel, in consultation with the Government contracting officer, may select other award instruments, as they deem appropriate. DARPA will apply publication or other restrictions, as necessary, if it determines that the research resulting from the proposed effort will present a high likelihood of disclosing performance characteristics of military systems or manufacturing technologies that are unique and critical to defense. Any award resulting from such a determination will include a requirement for DARPA permission before publishing any information or results on the program. For more information on publication restrictions, see the section below on Fundamental Research.

Fundamental Research

It is DoD policy that the publication of products of fundamental research will remain unrestricted to the maximum extent possible. National Security Decision Directive (NSDD) 189 established the national policy for controlling the flow of scientific, technical, and engineering information produced in federally funded fundamental research at colleges, universities, and laboratories. The Directive defines fundamental research as follows:

'Fundamental research' means basic and applied research in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization, the results of which ordinarily are restricted for proprietary or national security reasons.

As of the date of publication of this BAA, the Government expects that program goals as described herein may be met by proposers intending to perform fundamental research. The Government does not anticipate applying publication restrictions of any kind to individual awards for fundamental research that may result from this BAA. Notwithstanding this statement of expectation, the Government is not prohibited from considering and selecting research proposals that, while perhaps not qualifying as fundamental research under the foregoing definition, still meet the BAA criteria for submissions. If proposals are selected for award that offer other than a fundamental research solution, the Government will either work with the proposer to modify the proposed statement of work to bring the research back into line with fundamental research or else the proposer will agree to restrictions in order to receive an award.

Proposers should indicate in their proposal whether they believe the scope of the research included in their proposal is fundamental or not. While proposers should clearly explain the intended results of their research, the Government shall have sole discretion to select award instrument type and to negotiate all instrument terms and conditions with selectees. Appropriate clauses will be included in resultant awards for non-fundamental research to prescribe publication requirements and other restrictions, as appropriate.

For certain research projects, it may be possible that although the research being performed by the prime contractor is restricted research, a subawardee may be conducting fundamental research. In those cases, it is the prime contractor’s responsibility to explain in its proposal why its subawardee’s effort is fundamental research.

The following statement or similar provision will be incorporated into any resultant non-fundamental research procurement contract or other transaction:

There shall be no dissemination or publication, except within and between the contractor and any subawardees, of information developed under this contract or contained in the reports to be furnished pursuant to this contract without prior written approval of DARPA’s Public Release Center (DARPA/PRC). All technical reports will be given proper review by appropriate authority to determine which Distribution Statement is to be applied prior to the initial distribution of these reports by the contractor. With regard to subawardee proposals for Fundamental Research, papers resulting from unclassified fundamental research are exempt from prepublication controls and this review requirement, pursuant to DoD Instruction 5230.27 dated October 6, 1987.

When submitting material for written approval for open publication, the contractor/awardee must submit a request for public release to the DARPA/PRC and include the following information: (1) Document Information: document title, document author, short plain-language description of technology discussed in the material (approx.

30 words), number of pages (or minutes of video) and document type (e.g., briefing, report, abstract, article, or paper); (2) Event Information: event type (conference, principal investigator meeting, article or paper), event date, desired date for DARPA's approval; (3) DARPA Sponsor: DARPA Program Manager, DARPA office, and contract number; and (4) Contractor/Awardee's Information: POC name, email and phone. Allow four weeks for processing; due dates under four weeks require a justification. Unusual electronic file formats may require additional processing time. Requests may be sent either via email to public_release_center@darpa.mil or by mail at 675 North Randolph Street, Arlington VA 22203-2114, telephone (571) 218-4235. Refer to the following for link for information about DARPA’s public release process: http://www.darpa.mil/work-with-us/contract-management/public-release.”

III. Eligibility Information

All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA.

A. Eligible Applicants

Federally Funded Research and Development Centers (FFRDCs) and Government entities (e.g., Government/National laboratories, military educational institutions, etc.) are subject to applicable direct competition limitations and cannot propose to this BAA in any capacity unless they meet the following conditions: (1) FFRDCs must clearly demonstrate that the proposed work is not otherwise available from the private sector; and (2) FFRDCs must provide a letter on official letterhead from their sponsoring organization citing the specific authority establishing their eligibility to propose to Government solicitations and compete with industry, and their compliance with the associated FFRDC sponsor agreement’s terms and conditions. This information is required for FFRDCs proposing to be prime contractors or subawardees.

Government entities must clearly demonstrate that the work is not otherwise available from the private sector and provide written documentation citing the specific statutory authority and contractual authority, if relevant, establishing their ability to propose to Government solicitations. At the present time, DARPA does not consider 15 U.S.C. § 3710a to be sufficient legal authority to show eligibility. While 10 U.S.C.§ 2539b may be the appropriate statutory starting point for some entities, specific supporting regulatory guidance, together with evidence mailto:public_release_center@darpa.mil of agency approval, will still be required to fully establish eligibility. DARPA will consider FFRDC and Government entity eligibility submissions on a case-by-case basis; however, the burden to prove eligibility for all team members rests solely with the proposer.

Non-U.S. organizations and/or individuals may participate to the extent that such participants comply with any necessary nondisclosure agreements, security regulations, export control laws, and other governing statutes applicable under the circumstances.

B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and Organizational Conflicts of Interest

Current federal employees are prohibited from participating in particular matters involving conflicting financial, employment, and representational interests (18 U.S.C. §§ 203, 205, and 208). Once the proposals have been received, and prior to the start of proposal evaluations, the Government will assess potential conflicts of interest and will promptly notify the proposer if any appear to exist. The Government assessment does NOT affect, offset, or mitigate the proposer’s responsibility to give full notice and planned mitigation for all potential organizational conflicts, as discussed below.

Without prior approval or a waiver from the DARPA Director, in accordance with FAR 9.503, a contractor cannot simultaneously provide scientific, engineering, technical assistance (SETA) or similar support and also be a technical performer. As part of the proposal submission, all members of the proposed team (prime proposers, proposed subawardees, and consultants) must affirm whether they (their organizations and individual team members) are providing SETA or similar support to any DARPA technical office(s) through an active contract or subcontract. All affirmations must state which office(s) the proposer, subawardees, consultant, or individual supports and identify the prime contract number(s). All facts relevant to the existence or potential existence of organizational conflicts of interest (FAR 9.5) must be disclosed. The disclosure must include a description of the action the proposer has taken or proposes to take to avoid, neutralize, or mitigate such conflict. If in the sole opinion of the Government after full consideration of the circumstances, a proposal fails to fully disclose potential conflicts of interest and/or any identified conflict situation cannot be effectively mitigated, the proposal will be rejected without technical evaluation and withdrawn from further consideration for award.

If a prospective proposer believes a conflict of interest exists or may exist (whether organizational or otherwise) or has questions on what constitutes a conflict of interest, the proposer should send his/her contact information and a summary of the potential conflict via email to the BAA email address before time and effort are expended in preparing a proposal and mitigation plan.

C. Cost Sharing/Matching

Cost sharing is not required; however, it will be carefully considered where there is an applicable statutory condition relating to the selected funding instrument (e.g., for any Other Transactions under the authority of 10 U.S.C. § 2371). Cost sharing is encouraged where there is a reasonable probability of a potential commercial application related to the proposed research and development effort.

For more information on potential cost sharing requirements for Other Transactions for Prototype, see http://www.darpa.mil/work-with-us/contract-management#OtherTransactions.

D. Other Eligibility Criteria

1. Collaborative Efforts

Collaborative efforts/teaming are encouraged.

E. Associate Contractor Agreement (ACA) Clause

This same or similar clause will be included in all awards against DARPA-BAA-16-62:

(a) It is recognized that success of the CHIPS research effort depends in part upon the open exchange of information between the various Associate Contractors involved in the effort. This clause is intended to insure that there will be appropriate coordination and integration of work by the Associate Contractors to achieve complete compatibility and to prevent unnecessary duplication of effort. By executing this contract, the Contractor assumes the responsibilities of an Associate Contractor. For the purpose of this clause, the term Contractor includes subsidiaries, affiliates, and organizations under the control of the contractor (e.g. subcontractors).

(b) Work under this contract may involve access to proprietary or confidential data from an Associate Contractor. To the extent that such data is received by the Contractor from any Associate Contractor for the performance of this contract, the Contractor hereby agrees that any proprietary information received shall remain the property of the Associate Contractor and shall be used solely for the purpose of the CHIPS research effort. Only that information which is received from another contractor in writing and which is clearly identified as proprietary or confidential shall be protected in accordance with this provision. The obligation to retain such information in confidence will be satisfied if the Contractor receiving such information utilizes the same controls as it employs to avoid disclosure, publication, or dissemination of its own proprietary information. The receiving Contractor agrees to hold such information in confidence as provided herein so long as such information is of a proprietary/confidential or limited rights nature.

(c) The Contractor hereby agrees to closely cooperate as an Associate Contractor with the other Associate Contractors on this research effort. This involves as a minimum:

(1) Maintenance of a close liaison and working relationship;

(2) Maintenance of a free and open information network with all Government-identified

Associate Contractors;

(3) Delineation of detailed interface…