DARPA-BAA-15-55.pdf

Broad Agency Announcement Circuit Realization At Faster Timescales (CRAFT)

Microsystems Technology Office

DARPA-BAA-15-55

August 17, 2015

Table of Contents

PART I: OVERVIEW INFORMATION

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description II. Award Information III. Eligibility Information

A. Eligible Applicants B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and

Organizational Conflicts of Interest C. Cost Sharing/Matching D. Other Eligibility Criteria

1. Collaborative Efforts E. Associate Contractor Agreement Clause

IV. Application and Submission Information A. Address to Request Application Package B. Content and Form of Application Submission

1. Security Information

2. Proprietary Information

3. Proposal Submission Information

4. Full Proposal Format

5. Submission Dates and Times

6. Funding Restrictions

7. Other Submission Requirements

V. Application Review Information A. Evaluation Criteria B. Review and Selection Process

VI. Award Administration Information A. Selection Notices B. Administrative and National Policy Requirements

1. Meeting and Travel Requirements

2. Human Subjects Research

3. Animal Use

4. Export Control

5. Subcontracting

6. Electronic and Information Technology

7. Employment Eligibility Verification

8. Reserved

9. System for Award Management (SAM) and Universal Identifier Requirements

10. Reporting Executive Compensation and First-Tier Subcontract Awards

11. Updates of Information Regarding Responsibility Matters

12. Representations by Corporations Regarding an Unpaid Delinquent Tax Liability or a Felony Conviction under any Federal Law

13. Cost Accounting Standards (CAS) Notices and Certification

14. Controlled Unclassified Information (CUI) on Non-DoD Information Systems

15. Safeguarding of Unclassified Controlled Technical Information C. Reporting D. Electronic Systems

1. Representations and Certifications

2. Wide Area Work Flow (WAWF)

3. i-Edison

VII. Agency Contacts VIII. Other Information

A. Intellectual Property Procurement Contract Proposers

1. Noncommercial Items (Technical Data and Computer Software)

2. Commercial Items (Technical Data and Computer Software)

B. Non-Procurement Contract Proposers – Noncommercial and Commercial Items (Technical Data and Computer Software)

C. All Proposers – Patents D. All Proposers – Intellectual Property Representations E. Other Transactions (OTs):

PART I: OVERVIEW INFORMATION

Federal Agency Name – Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO)

Funding Opportunity Title – Circuit Realization At Faster Timescales (CRAFT) Announcement Type – Initial Announcement Funding Opportunity Number – DARPA-BAA-15-55 Catalog of Federal Domestic Assistance Numbers (CFDA) – 12.910 Research and

Technology Development Dates:

o Posting Date: 17 August 2015 o Proposal Due Date: 5 October 2015 o Estimated period of performance start: February, 2016

Concise description of the funding opportunity: DARPA seeks to develop a custom integrated circuit design flow and methodology that will: 1) sharply reduce the amount of effort required to design high-performance custom integrated circuits, 2) greatly facilitate porting of integrated circuit designs to secondary foundries and/or more advanced technology nodes, and 3) strongly increase reuse of integrated circuit elements (IP).

Total amount of money available to be awarded: Approximately $30M-$35M Anticipated individual awards – Multiple awards are anticipated.

Anticipated funding type - 6.1, and/or 6.2 Types of instruments that may be awarded – Procurement contract, grant, cooperative agreement or other transaction.

Any cost sharing requirements – None.

Agency contact o Dr. Linton Salmon, Program Manager BAA Coordinator: DARPA-BAA-15-55@darpa.mil

DARPA/MTO

ATTN: DARPA-BAA-15-55

675 North Randolph Street Arlington, VA 22203-2114

FAX: (703) 807-9926

EMAIL: DARPA-BAA-15-55@darpa.mil

PROPOSERS ARE CAUTIONED THAT EVALUATION RATINGS MAY BE LOWERED

AND/OR PROPOSALS REJECTED IF PROPOSAL PREPARATION (PROPOSAL FORMAT,

CONTENT, ETC.) AND/OR SUBMITTAL INSTRUCTIONS ARE NOT FOLLOWED.

THOSE INTENDING TO SUBMIT A PROPOSAL FOR AN ASSISTANCE INSTRUMENT

(GRANT OR COOPERATIVE AGREEMENT) ARE STRONGLY ENCOURAGED TO READ

THE INSTRUCTIONS PROVIDED AT SECTION IV(B)(4) REGARDING THE TIME

REQUIRED TO RECEIVE VALIDATION OF SUBMISSIONS MADE THROUGH

mailto:name@darpa.mil

GRANTS.GOV. PROPOSALS THAT ARE VALIDATED AFTER THE PROPOSAL DUE

DATE/TIME WILL BE CONSIDERED LATE AND, AS SUCH, WILL NOT BE REVIEWED.

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description

The Defense Advanced Research Projects Agency often selects its research efforts through the Broad Agency Announcement (BAA) process. This BAA is being issued, and any resultant selection will be made, using procedures under Federal Acquisition Regulation (FAR) 35.016 and the Department of Defense Grant and Agreement Regulatory System (DoDGARS) Part 22 for Grants and Cooperative Agreements. Any negotiations and/or awards will use procedures under FAR 15.4, Contract Pricing, as specified in the BAA (including DoDGARS Part 22 for Grants and Cooperative Agreements). Proposals received as a result of this BAA shall be evaluated in accordance with evaluation criteria specified herein through a scientific review process.

DARPA BAAs are posted on the Federal Business Opportunities (FedBizOpps) website, http://www.fbo.gov/, and, as applicable, the Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA.

DARPA is soliciting innovative research and development (R&D) proposals to develop a custom integrated circuit design flow and methodology that will: 1) sharply reduce the amount of effort required to design high-performance custom integrated circuits, 2) greatly facilitate porting of integrated circuit designs to secondary foundries and/or more advanced technology nodes, and 3) strongly increase reuse of integrated circuit elements (IP).

A. Background

To maintain technology dominance, the Department of Defense (DoD) is developing next generation systems that require high computational performance in a power-constrained environment. For example, to meet modern mission requirements, the computational needs of Unmanned Aerial Vehicle (UAV) systems are increasing while the power budget available for that computation is increasingly constrained. In addition, system flexibility and budget constraints drive the need for quick turn-around development of the integrated circuits that provide high system computation capability. Currently, the DoD cannot have both the highest possible performance within the system-defined integrated circuit power budget, or performance at power (PAP), and fast implementation. We must choose between a high performing, custom integrated circuit solution that requires years to design and fabricate using the current, commercially available ASIC design flow, or a >100X lower performing general purpose integrated circuit solution that can be programmed in months. This dilemma has reduced utilization of custom integrated circuits and subsequently, performance of DoD systems.

CRAFT seeks to break this paradigm by developing a custom integrated circuit design flow and methodology that will sharply reduce the amount of effort required to design a custom integrated http://www.fbo.gov/ http://www.grants.gov/ circuit while preserving integrated circuit PAP. CRAFT will demonstrate the effectiveness of these methodologies through implementation in a commercial, leading-edge 16nm/14nm technology node. In addition, CRAFT seeks to demonstrate the ability to quickly and reliably port designs to new foundry process flows and to more advanced silicon technology process flows.

Finally, CRAFT seeks to increase reuse and design leverage by providing a repository for secure storage and distribution of design elements (IP) and methodologies.

B. Program Objective

The program objective for CRAFT is to sharply reduce the barriers to DoD use of custom integrated circuits built using leading-edge CMOS technology while maintaining the high level of PAP promised by this technology.

Figure 1A-1

Figure 1A-1 summarizes the current situation for 28nm technology. It takes on the order of 2.5 years to design and fabricate a custom integrated circuit design for DoD. 40% of the time is absorbed by 2 spins of fabrication and 60% is absorbed by design. 60% of the design time (or 36% of the total time) is spent in design verification. All three of these components must be reduced in order to meet the targets of CRAFT as shown in the second bar of Figure 1A-1.

CRAFT seeks proposals to reduce the barriers facing design teams for DoD custom integrated circuits and enable increased DoD use of custom integrated circuits by addressing key issues such as the following:

An integrated circuit design flow that reduces the effort required to design/verify a custom integrated circuit by a factor of 10X

Increased reuse (DoD and 3rd party IP) and lowered level of manpower and design expertise required to design and verify integrated circuits in leading-edge CMOS technology

Embedding of design and process complexity into circuit components (macros, sub-circuits, generators, compilers) that are designed/verified once and reused many times

Methods to quickly and easily port custom integrated circuit designs from one foundry process to another similar foundry/process and/or migrate designs to a more advanced CMOS technology node

Methods to increase reuse by improving the definition, secure storage, and distribution of key design components such as macros, generators, compilers, IP, and technology information

CRAFT does NOT seek proposals for the following:

Total replacement of the existing ASIC design methodology without consideration of existing EDA tools

Development of a new high-level design description language such as Scala or Python Development of new database architectures New methods of CMOS fabrication

C. Program Structure

DARPA has identified three barriers to using leading-edge CMOS technology to build custom integrated circuits: 1) lengthy and expensive design, verification, and fabrication cycles; 2) difficulty migrating designs from one foundry process to another; and, 3) lack of reusability in DoD designs. These barriers align with the three technical areas of this BAA.

A single proposal may address only one of the following:

(a) Both Technical Area 1 and Technical Area 2

(b) Only Technical Area 3

(c) All three technical areas: Technical Area 1, Technical Area 2, and Technical Area 3

Proposals that address more than one technical area must be constructed so that tasks dedicated to each technical area can be selected independently from one another. Proposals will be evaluated against each technical area separately regardless of the number of technical areas included in the proposal. TA-1 and TA-3 have three phases. TA-2 does not have a Phase 1 and begins with Phase 2.

Dollar amounts associated with each of the technical areas are included in the discussion below only as rough guides to the relative scope of the respective efforts. As indicated in Section II, the amount of resources made available under this BAA will depend on the quality of the proposals received and the availability of funds.

Wafer Fabrication:

Note that DARPA will provide fabrication support through a number of separately funded multi-project runs and therefore, fabrication costs should not be included in proposal budgets. As shown in Figure 1C-1, proposers for Technical Area 1 should assume 4 fabrication runs at a primary commercial 16nm/14nm foundry. Proposers for Technical Area 2 should assume one fabrication run at a secondary 16nm/14nm foundry during each of Phase II and Phase III and one fabrication run at a more advanced foundry during each of Phase II and Phase III.

Figure 1C-1 Approximate Wafer Fabrication Schedule

D. Technical Areas

Technical Area 1 – Design

The primary goal of TA-1 is to develop a reference design flow that can demonstrate a 10X reduction in design effort for a representative DoD custom integrated circuit design while maintaining 90% of the PAP when compared to a traditional standard-cell based design.

The design flow should have the following characteristics:

Correct by construction or heavily automated design verification over full design/process corners

Circuit representation in an existing high-level language that:

o Enables circuit architecture exploration o Hides process technology complexity o Is usable by system engineers who may not be expert circuit designers o Is consistent with co-development of software and hardware

Robustness as measured by first pass design success Extensive reuse of design components and design effort o Reuse through generators or compilers o Definition of key high-level design macros/generators o Characterization of key, high-level design macros/generators o Seamless integration of design components provided by 3rd parties

Applicable to design of System on a Chip (SoC) integrated circuits. That is, applicable to integrated circuits that have multiple digital, analog, mixed-signal, and memory components.

Support for designs fabricated using the DARPA-selected commercial 16nm/14nm foundry/process flow.

Effectiveness of the design flow will be demonstrated in a commercial 16nm/14nm foundry technology, using DARPA-defined reference designs and testing of fabricated hardware.

The critical research questions that should be addressed for this area are:

1. How can the design flow ensure that custom integrated circuit designs are functional and robust without extensive verification?

2. What is the set of macros or generators required to support the program goals for design efficiency across application areas?

3. How can the design flow ensure seamless utilization of existing 3rd party IP to maximize reuse and minimize verification?

4. How should the macros, generators, and IP be represented in the design flow?

5. What is the best high-level circuit representation that allows design flow robustness, architecture exploration, and hardware-software co-optimization?

6. How will you ensure that the design flow, methods, and IP developed in TA-1 are effectively stored and distributed through the CRAFT repository?

TA-1 Program Deliverables

Phase I (15 months) – At the conclusion of Phase I, performers should have demonstrated a 10X reduction in the design effort required to create a design using a standard flow for an SoC of their choosing with the following characteristics:

Logic block size of > 200k gates Multiple mixed signal blocks Multiple SRAM memory blocks Multiple 3rd party IP blocks

Note that design results will be weighted by the difficulty (complexity of logic functions, number/complexity of analog blocks, number/variety of embedded memory blocks) of the performer-chosen design.

Deliverables:

Report documenting successful simulation of chip functionality across standard process, temperature, and voltage corner cases The macros/generators sufficient to design the performer-selected integrated circuit as well as a broad range of other, similar integrated circuits Any unique software tools required to instantiate the design

A fully documented reference CAD flow, including any required validation

Phase II (12 months) – At the conclusion of Phase II, performers should have demonstrated a 7X reduction in the design effort to create a full, DARPA-selected DoD SoC design. Successful performers also will have provided sufficient documentation of the design flow to enable external, expert design groups to design full, DoD relevant designs.

Deliverables:

Complete testing of fabricated chip functionality across the standard temperature range Full hardware characterization and documentation of an initial suite of macros/generators A fully documented reference CAD flow, including any required validation steps Definition and design of a full suite of macro/generators

Phase III (12 months) – At the conclusion of Phase III, performers should have defined and fully documented a complete reference flow, capable of being used to design a DARPA-selected DoD custom integrated circuit design that is fabricated and confirmed through hardware testing.

Performers are also expected to provide their design flow and support to a group of independently funded teams who will design multiple DoD-specific custom integrated circuits that will be fabricated, and confirmed through hardware testing.

Deliverables:

Complete testing of the functionality of multiple fabricated integrated circuits Full hardware characterization of a full suite of macros/generators A complete, fully documented reference CAD flow that has been exercised by multiple external design groups Successful completion of a design challenge using the documented reference design flow Plan for continued distribution, maintenance, and improvement of the reference design flow after program completion

The timeline for TA-1 is shown in Figure 1C-1. TA-1 has three phases. Phase I is 15 months, Phase II is 12 months, and Phase III is 12 months in duration.

Figure 1D-1: Timeline of TA-1 (39 months total)

Technical Area 2 – Port/Migrate

The dynamic commercial environment for silicon integrated circuit fabrication drives a strong need for the DoD to have multiple suppliers for leading-edge silicon CMOS integrated circuits.

The number of suppliers of leading-edge CMOS foundry services has dropped over the past 10 years from more than 13 companies to total of 4 and there are indications that consolidation will continue. As a result, DoD cannot depend on any one foundry/process being available for the decades long life-cycle of a DoD system. The answer to this problem is to have a facilitated method to retarget custom integrated circuit designs from one foundry/process to another. However, due to the complexity of leading-edge CMOS technology, current design retargeting methods require ~ 80% of the effort that was required to make the original design. This level of cost is not feasible for DoD applications and therefore, a more efficient retargeting method is needed.

The major purpose of this technical area is to ensure multiple sources of leading-edge CMOS fabrication by developing a custom integrated circuit design flow that can take an integrated circuit that was designed to be fabricated in a primary foundry/flow, and port the design to a secondary foundry/flow with less than 20% of the effort required to design the integrated circuit for the primary foundry/flow.

Another limitation for DoD use of custom integrated circuits is the current slow and costly methodology used to migrate designs from one foundry/flow to a more advanced CMOS flow used at either the primary or secondary foundries. In general, the integrated circuit is completely re-designed as part of the effort. A secondary purpose of this technical area will be to develop a design flow that will sharply reduce the effort required to migrate a design from one technology node to a more advanced node.

The port/migrate flow should have the following characteristics:

Derived from the design flow developed in TA-1.

Enables porting of a representative design from a primary foundry/flow to a secondary foundry/flow with < 20% of the effort required for the original design Requires minimal manually-driven verification for the ported design Ensures first time fabrication success of the ported design Enables migration of a representative design from the primary foundry/flow to a more advanced flow using the primary or a secondary foundry with < 50% of the effort required for the original design.

Effectiveness of the port and the migrate design flows will be demonstrated using commercial foundry technology, defined reference designs, and testing of fabricated hardware in the secondary foundry/technology node.

The critical research questions that should be addressed for this area are:

1. What hardware characterization tasks are required at the primary and secondary foundries to ensure appropriate transfer of design primitives to a new flow or a more advanced technology node?

2. How can porting and/or migration be accomplished without requiring new synthesis or new pre-schematic verification?

3. What simulation, hardware characterization, or verification is required to ensure equivalence of designs fabricated at the primary and secondary foundries?

4. How will you ensure that the design flow, methods, and IP developed in TA-2 are effectively stored and distributed through the repository?

TA-2 Program Deliverables

Phase I - None

Phase II (12 months) – At the conclusion of Phase II, performers should have designed and fabricated an initial set of design primitives/macros in a secondary foundry/process flow and in a more advanced foundry/process node.

Deliverables:

Design and documentation of an initial set of design primitives/macros at a DARPA-selected, secondary 16nm/14nm foundry/process flow Fabrication of the initial primitive/macros at the secondary foundry Design using the porting flow and subsequent fabrication of a performer-selected SoC design in the secondary 16nm/14nm foundry/process flow.

Design and documentation of an initial set of design primitives/macros in a DARPA-selected more advanced foundry/process flow Fabrication of those primitive/macros using the more advanced process flow Design, using the migration flow, and subsequent fabrication of a performer-selected SoC design in the DARPA-selected more advanced foundry/process

Phase III (12 months) – At the conclusion of Phase III, performers should have fully characterized a full set of design primitives/macros in a secondary foundry/process flow and in a more advanced foundry/process node. The performer should also have demonstrated the successful use of the porting and migration flows to design and fabricate a full, DARPA-selected, DoD SoC integrated circuit.

Deliverables:

Design and documentation for a full set of design primitives/macros at a DARPA-selected secondary 16nm/14nm foundry/process flow Fabrication of the full set of primitive/macros at the secondary foundry Design using the porting flow and subsequent fabrication of a DARPA-selected, DoD SoC design at the secondary foundry Design and documentation of a full set of design primitives/macros in a DARPA-selected more advanced foundry/process flow Fabrication of those primitive/macros using the more advanced process flow Design using the migration flow and subsequent fabrication of a DARPA-selected, DoD

SoC design in the DARPA-selected more advanced foundry/process

The timeline for TA-2 is shown in Figure 1C-2. TA-2 has two Phases. Phase II is 12 months, and Phase III is 12 months in duration.

Figure 1D-2: Timeline of TA-2 (24 months total)

Approximately $26M total is available for submissions to technical areas TA-1 and TA-2; multiple awards are anticipated.

Technical Area 3 – Repository

Achieving the goals of TA-1 and TA-2 will require heavy reuse of design primitives, methods, and information. Reuse, in turn, requires services that provide for data ingest, discovery, distribution, and secure access for the elements to be reused. The purpose of this task is to establish a common cyber-infrastructure approach, a trusted repository, and to define the data management plans and methods required to submit, secure, and distribute the information. Prospective performers are referred to international standards ISO 14721:2012 (Open Archival Information System (OAIS)) and CCSDS 652.0-M-1 (Audit and Certification of Trustworthy Digital Repositories) for further context.

The repository should have the following characteristics:

Technologies to support representation of and transformation among multiple types of data:

design data, characterization data, design representations, design flow scripts and software, technology information and associated provenance for each of the above.

Mechanisms for providing information assurance and security to this data to protect against practical threats to its authenticity, integrity, and non-reputability both while in motion and while at rest.

An organization or process that can establish, define and manage the evolution standards for the content of the trusted repository.

Structure for governance to receive advice on the most critical content to be included in the repository.

Establishment of a set of data management guidelines and policies, including processes and procedures for submission of data to the repository from government and commercial entities.

Extensive reuse of existing frameworks and software technologies for deploying cyber-infrastructure to support data-driven science and engineering, including: federated storage approaches, grid storage middleware, portals and collaboration, process capture and workflow management tools, and software for data tilling and schema management.

The critical research questions that should be addressed for this area are:

1. What is the maximum leverage a trusted repository can have from the existing developments and technologies in cyber-infrastructure for data science? (NSF 07-28, Cyberinfrastructure Vision for 21st Century Discovery)

2. What are the most efficient means to secure repository content to users?

3. How can repository data be secured while maintaining maximum usability?

4. What delivery methods can be instituted to reduce costs of 3rd party IP and EDA tools?

5. How will you ensure that 3rd party IP and EDA tools as well as the design flow, methods, and IP developed in TA-1 and TA-2 are effectively stored and distributed through this repository?

TA-3 Program Deliverables

Phase I (15 months) – At the conclusion of Phase I, performers should have established the organization of the repository, including the basic IT infrastructure, the initial data structure, and the government/industry advisory board.

Deliverables:

Definition of the structure of the IT infrastructure supporting the repository Structure for governance of the repository, including establishment of a industry/government advisory board Initial definition of the format/criteria for content submission to the repository A plan and guidelines for submission of 3rd party IP to the repository

Phase II (12 months) – At the conclusion of Phase II, performers should have exercised the repository to support full designs.

Deliverables:

Storage and distribution of the design elements (primitives/macros, software, methods, etc.) developed by all TA-1 and TA-2 performers.

Summary of the repository needs as defined by the government/industry repository advisory board and users of the repository o Methods of use of the repository o Definition of the appropriate content for the repository (Design flow, IP, data)

Performer will not be responsible for acquisition of the content, only the definition

Final definition of the format/criteria for content submission to the repository A plan for continuation and sustainability of the repository after program completion

Phase III (12 months) – At the conclusion of Phase III, performers should have refined the organization of the repository and its content and developed a plan for its continuation after program completion.

Deliverables:

Storage and distribution of the design elements (primitives/macros, software, methods, etc.) developed in TA-1 and TA-2 Demonstration of extensive use of the repository by multiple DoD performer users Implementation of the plan for continuation and sustainability of the repository after program completion

The timeline for TA-3 is shown in Figure 1C-3. TA-3 has three Phases. Phase I is 15 months, Phase II is 12 months, and Phase III is 12 months in duration.

Figure 1D-3: Timeline of TA-3 (39 months total)

Approximately $3M total is available for this technical area; one award is anticipated.

E. Metrics

Although the metrics below will be used to measure performer progress, proposers are encouraged to propose additional metrics for evaluation of their success.

Technical Area 1 Each performing team should have demonstrated the following rate of design of fully validated equivalent gates/day for a new, representative, custom DoD System on a Chip (SoC) integrated circuit while maintaining no less than 90% of the technology entitlement

PAP:

o Phase I – 50k gates/engineer-day o Phase II – 75k gates/engineer-day o Phase III – 100k gates/engineer-day

Each performing team should have demonstrated the following rate of design of analog blocks for a new, representative, custom DoD SoC integrated circuit while maintaining no less than 90% of the technology entitlement PAP:

o Phase I – 1.0 analog blocks/engineer-week o Phase II – 1.3 analog functions/engineer-week o Phase III – 1.5 analog functions/engineer-week

Each performing team should have demonstrated the following reduction in design effort for a new, representative, custom DoD SoC integrated circuit when compared with a design made using the current standard cell design flow and while maintaining no less than 90% of the technology entitlement PAP:

o Phase I – 5X reduction o Phase II – 7X reduction o Phase III – 10X reduction

By the end of the program, each performing team should have demonstrated the following:

o Reduction in total design costs to less than $2M for a single, representative, custom

DoD SoC design Random logic block size of > 50M gates Multiple mixed signal blocks Multiple SRAM memory blocks o Top level chip verification time of less than 1 week, including DRC and LVS

Note that design results will be weighted by the difficulty (complexity of logic functions, number/complexity of analog blocks, number/variety of embedded memory blocks) of the performer-chosen design.

Technical Area 2 Each performing team should have demonstrated the following:

o Porting of a custom design from a 16nm/14nm flow at the primary foundry to a same-node 16nm/14nm flow at the secondary foundry with less than 20% of the effort required for the original OOD design while maintaining the PAP of the original design:

Phase II: Performer-selected design Phase III: DARPA-selected design o Migration of an existing custom design from a 16nm/14nm flow at the primary foundry to a more advanced node flow with less than 50% of the effort required for the original OOD design while maintaining no less than 90% of the technology entitlement PAP:

Phase II: Performer-selected design Phase III: DARPA-selected design

Table 1 – Summary of Evaluation Components

Technical Area 3

Each performing team should have demonstrated the following average percentage of a representative custom DoD integrated circuit die area filled with reused functions retrieved from the repository:

o Phase II – 30% o Phase III – 50%

II. Award Information

Multiple awards are anticipated. The amount of resources made available under this BAA will depend on the quality of the proposals received and the availability of funds.

The Government reserves the right to select for negotiation all, some, one, or none of the proposals received in response to this solicitation, and to make awards without discussions with proposers. The Government also reserves the right to conduct discussions if it is later determined to be necessary. If warranted, portions of resulting awards may be segregated into pre-priced options. Additionally, DARPA reserves the right to accept proposals in their entirety or to select only portions of proposals for award. In the event that DARPA desires to award only portions of a proposal, negotiations may be opened with that proposer. The Government reserves the right to fund proposals in phases with options for continued work at the end of one or more of the phases.

Awards under this BAA will be made to proposers on the basis of the evaluation criteria listed below (see section labeled “Application Review Information”, Sec. V.), and program balance to provide overall value to the Government. The Government reserves the right to request any additional, necessary documentation once it makes the award instrument determination. Such additional information may include but is not limited to Representations and Certifications. The Government reserves the right to remove proposers from award consideration should the parties fail to reach agreement on award terms, conditions and cost/price within a reasonable time or the proposer fails to timely provide requested additional information. Proposals identified for negotiation may result in a procurement contract, grant, cooperative agreement, or other transaction, depending upon the nature of the work proposed, the required degree of interaction between parties, whether or not the research is classified as Fundamental Research, and other factors.

In all cases, the Government contracting officer shall have sole discretion to select award instrument type and to negotiate all instrument terms and conditions with selectees. Proposers are advised that if they propose grants or cooperative agreements, DARPA may select other award instruments, as it deems appropriate. DARPA will apply publication or other restrictions, as necessary, if it determines that the research resulting from the proposed effort will present a high likelihood of disclosing performance characteristics of military systems or manufacturing technologies that are unique and critical to defense. Any award resulting from such a determination will include a requirement for DARPA permission before publishing any information or results on the program. For more information on publication restrictions, see the section below on Fundamental Research.

Fundamental Research

It is DoD policy that the publication of products of fundamental research will remain unrestricted to the maximum extent possible. National Security Decision Directive (NSDD) 189 established the national policy for controlling the flow of scientific, technical, and engineering information produced in federally funded fundamental research at colleges, universities, and laboratories. The Directive defines fundamental research as follows:

'Fundamental research' means basic and applied research in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization, the results of which ordinarily are restricted for proprietary or national security reasons.

As of the date of publication of this BAA, the Government expects that program goals as described herein may be met by proposers intending to perform fundamental research. The Government does not anticipate applying publication restrictions of any kind to individual awards for fundamental research that may result from this BAA. Notwithstanding this statement of expectation, the Government is not prohibited from considering and selecting research proposals that, while perhaps not qualifying as fundamental research under the foregoing definition, still meet the BAA criteria for submissions. If proposals are selected for award that offer other than a fundamental research solution, the Government will either work with the proposer to modify the proposed statement of work to bring the research back into line with fundamental research or else the proposer will agree to restrictions in order to receive an award.

Proposers should indicate in their proposal whether they believe the scope of the research included in their proposal is fundamental or not. While proposers should clearly explain the intended results of their research, the Government shall have sole discretion to select award instrument type and to negotiate all instrument terms and conditions with selectees. Appropriate clauses will be included in resultant awards for non-fundamental research to prescribe publication requirements and other restrictions, as appropriate.

For certain research projects, it may be possible that although the research being performed by the prime contractor is restricted research, a subawardee may be conducting contracted fundamental research. In those cases, it is the prime contractor’s responsibility to explain in its proposal why its subawardee’s effort is contracted fundamental research.

The following statement or similar provision will be incorporated into any resultant non-fundamental research procurement contract or other transaction:

“There shall be no dissemination or publication, except within and between the contractor and any subawardees, of information developed under this contract or contained in the reports to be furnished pursuant to this contract without prior written approval of DARPA’s Public Release Center (DARPA/PRC). All technical reports will be given proper review by appropriate authority to determine which Distribution Statement is to be applied prior to the initial distribution of these reports by the contractor. With regard to subawardee proposals for Contracted Fundamental Research, papers resulting from unclassified contracted fundamental research are exempt from prepublication controls and this review requirement, pursuant to DoD Instruction 5230.27 dated October 6, 1987.

When submitting material for written approval for open publication, the contractor/awardee must submit a request for public release to the DARPA/PRC and include the following information: (1) Document Information: document title, document author, short plain-language description of technology discussed in the material (approx.

30 words), number of pages (or minutes of video) and document type (e.g., briefing, report, abstract, article, or paper); (2) Event Information: event type (conference, principal investigator meeting, article or paper), event date, desired date for DARPA's approval; (3) DARPA Sponsor: DARPA Program Manager, DARPA office, and contract number; and (4) Contractor/Awardee's Information: POC name, email and phone. Allow four weeks for processing; due dates under four weeks require a justification. Unusual electronic file formats may require additional processing time. Requests may be sent either via email to prc@darpa.mil or by mail at 675 North Randolph Street, Arlington VA 22203-2114, telephone (571) 218-4235. Refer to the following for link for information about DARPA’s public release process: http://www.darpa.mil/work-with-us/contract-management/public-release.”

mailto:prc@darpa.mil

III. Eligibility Information

All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA.

A. Eligible Applicants Federally Funded Research and Development Centers (FFRDCs) and Government entities (e.g., Government/National laboratories, military educational institutions, etc.) are subject to applicable direct competition limitations and cannot propose to this BAA in any capacity unless they meet the following conditions: (1) FFRDCs must clearly demonstrate that the proposed work is not otherwise available from the private sector; and (2) FFRDCs must provide a letter on official letterhead from their sponsoring organization citing the specific authority establishing their eligibility to propose to Government solicitations and compete with industry, and their compliance with the associated FFRDC sponsor agreement and terms and conditions. This information is required for FFRDCs proposing to be prime contractors or subawardees.

Government entities must clearly demonstrate that the work is not otherwise available from the private sector and provide written documentation citing the specific statutory authority and contractual authority, if relevant, establishing their ability to propose to Government solicitations. At the present time, DARPA does not consider 15 U.S.C. § 3710a to be sufficient legal authority to show eligibility. While 10 U.S.C.§ 2539b may be the appropriate statutory starting point for some entities, specific supporting regulatory guidance, together with evidence of agency approval, will still be required to fully establish eligibility. DARPA will consider FFRDC eligibility submissions on a case-by-case basis; however, the burden to prove eligibility for all team members rests solely with the proposer.

Non-U.S. organizations and/or individuals may participate to the extent that such participants comply with any necessary nondisclosure agreements, security regulations, export control laws, and other governing statutes applicable under the circumstances.

B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and Organizational Conflicts of Interest

Current federal employees are prohibited from participating in particular matters involving conflicting financial, employment, and representational interests (18 U.S.C. §§ 203, 205, and 208). Once the proposals have been received, and prior to the start of proposal evaluations, the Government will assess potential conflicts of interest and will promptly notify the proposer if any appear to exist. The Government assessment does NOT affect, offset, or mitigate the proposer’s responsibility to give full notice and planned mitigation for all potential organizational conflicts, as discussed below.

Without prior approval or a waiver from the DARPA Director, in accordance with FAR 9.503, a contractor cannot simultaneously provide scientific, engineering, technical assistance (SETA) or similar support and also be a technical performer. As part of the proposal submission, all members of the proposed team (prime proposers, proposed subawardees, and consultants) must affirm whether they (their organizations and individual team members) are providing SETA or similar support to any DARPA technical office(s) through an active contract or subcontract. All affirmations must state which office(s) the proposer, subawardees, consultant, or individual supports and identify the prime contract number(s). All facts relevant to the existence or potential existence of organizational conflicts of interest (FAR 9.5) must be disclosed. The disclosure must include a description of the action the proposer has taken or proposes to take to avoid, neutralize, or mitigate such conflict. If in the sole opinion of the Government after full consideration of the circumstances, a proposal fails to fully disclose potential conflicts of interest and/or any identified conflict situation cannot be effectively mitigated, the proposal will be rejected without technical evaluation and withdrawn from further consideration for award.

If a prospective proposer believes a conflict of interest exists or may exist (whether organizational or otherwise) or has questions on what constitutes a conflict of interest, the proposer should send his/her contact information and a summary of the potential conflict via email to the BAA email address before time and effort are expended in preparing a proposal and mitigation plan.

C. Cost Sharing/Matching Cost sharing is not required; however, it will be carefully considered where there is an applicable statutory condition relating to the selected funding instrument (e.g., for any Other Transactions under the authority of 10 U.S.C. § 2371). Cost sharing is encouraged where there is a reasonable probability of a potential commercial application related to the proposed research and development effort.

D. Other Eligibility Criteria

1. Collaborative Efforts

Collaborative efforts/teaming are encouraged.

E. Associate Contractor Agreement Clause

This same or similar clause will be included in all awards against DARPA-BAA-15-55:

(a) It is recognized that success of the CRAFT research effort depends in part upon the open exchange of information between the various Associate Contractors involved in the effort. This clause is intended to insure that there will be appropriate coordination and integration of work by the Associate Contractors to achieve complete compatibility and to prevent unnecessary duplication of effort. By executing this contract, the Contractor assumes the responsibilities of an Associate Contractor. For the purpose of this clause, the term Contractor includes subsidiaries, affiliates, and organizations under the control of the contractor (e.g. subcontractors).

(b) Work under this contract may involve access to proprietary or confidential data from an Associate Contractor. To the extent that such data is received by the Contractor from any Associate Contractor for the performance of this contract, the Contractor hereby agrees that any proprietary information received shall remain the property of the Associate Contractor and shall be used solely for the purpose of the CRAFT research effort. Only that information which is received from another contractor in writing and which is clearly identified as proprietary or confidential shall be protected in accordance with this provision. The obligation to retain such information in confidence will be satisfied if the Contractor receiving such information utilizes the same controls as it employs to avoid disclosure, publication, or dissemination of its own proprietary information. The receiving Contractor agrees to hold such information in confidence as provided herein so long as such information is of a proprietary/confidential or limited rights nature.

(c) The Contractor hereby agrees to closely cooperate as an Associate Contractor with the other Associate Contractors on this research effort. This involves as a minimum:

(1) Maintenance of a close liaison and working relationship;

(2) Maintenance of a free and open information network with all Government-identified Associate Contractors;

(3) Delineation of detailed interface responsibilities;

(4) Entering into a written agreement with the other Associate Contractors setting forth the substance and procedures relating to the foregoing, and promptly providing the Agreements Officer/Procuring Contracting Officer with a copy of same; and,

(5) Receipt of proprietary information from the Associate Contractor and transmittal of Contractor proprietary information to the Associate Contractors subject to any applicable proprietary information exchange agreements between associate contractors when, in either case, those actions are necessary for the performance of either.

(d) In the event that the Contractor and the Associate Contractor are unable to agree upon any such interface matter of substance, or if the technical data identified is not provided as scheduled, the Contractor shall promptly notify the DARPA CRAFT Program Manager. The Government will determine the appropriate corrective action and will issue guidance to the affected Contractor.

(e) The Contractor agrees to insert in all subcontracts hereunder which require access to proprietary information belonging to the Associate Contractor, a provision which shall conform substantially to the language of this clause, including this paragraph (e).

(f) Associate Contractors for this CRAFT research effort include:

Contractor Area

Note: It is intended that ACA’s be established, after selections and prior to contract award, between each TA-1/TA-2 performer and the TA-3 performer.

IV. Application and Submission Information

A. Address to Request Application Package This solicitation contains all information required to submit a proposal. No additional forms, kits, or other materials are needed. This notice constitutes the total BAA solicitation. No additional information is available, except as provided at FBO.gov or Grants.gov, nor will a formal Request for Proposal (RFP) or additional solicitation regarding this announcement be issued. Requests for the same will be disregarded.

B. Content and Form of Application Submission

DARPA policy is to treat all submissions as source selection information (see FAR 2.101 and 3.104), and to disclose their contents only for the purpose of evaluation. Restrictive notices notwithstanding, during the evaluation process, submissions may be handled by support contractors for administrative purposes and/or to assist with technical evaluation. All DARPA support contractors performing this role are expressly prohibited from performing DARPA-sponsored technical research and are bound by appropriate nondisclosure agreements.

Submissions will not be returned. The original of each submission received will be retained at DARPA and all other non-required copies destroyed. A certification of destruction may be requested, provided the formal request is received at this office within 5 days after unsuccessful notification.

1. Security Information

Classified submissions shall be transmitted in accordance with the following guidance.

Additional information on the subjects discussed in this section may be found at http://www.dss.mil/.

If a submission contains Classified National Security Information as defined by Executive Order 13526, the information must be appropriately and conspicuously marked with the proposed classification level and declassification date. Similarly, when the classification of a submission is in question, the submission must be appropriately and conspicuously marked with the proposed classification level and declassification date. Submissions requiring DARPA to make a final classification determination shall be marked as follows:

“CLASSIFICATION DETERMINATION PENDING. Protect as though classified____________________________(insert the recommended classification level, e.g., Top Secret, Secret or Confidential)”

NOTE: Classified submissions must indicate the classification level of not only the submitted materials, but also the classification level of the anticipated award.

Proposers submitting classified information must have, or be able to obtain prior to contract award, cognizant security agency approved facilities, information systems, and appropriately cleared/eligible personnel to perform at the classification level proposed. All proposer personnel performing Information Assurance (IA)/Cybersecurity related duties on classified Information Systems shall meet the requirements set forth in DoD Manual 8570.01-M (Information Assurance Workforce Improvement Program).

Proposers choosing to submit classified information from other collateral classified sources (i.e., sources other than DARPA) must…