Collaborative research: SHF: scalable cross-layer CO-design for stable mixed-precision acceleration

The National Science Foundation Division of Information and Intelligent Systems awarded the Trustees of Boston University $394,792 on January 1, 2027, under the Computer and Information Science and Engineering program (CFDA 47.070) to develop a cross-layer co-design framework for stable mixed-precision acceleration in computing hardware and software.

The project addresses numerical precision tradeoffs in high-performance computing workloads including physical artificial intelligence applications such as real-time robot control, large-scale neural network training, power grid management, and quantum physics simulation. The work combines numerical precision analysis with control theory to generate streamlined accelerator hardware designs and optimized code with provable stability guarantees. Boston University will design a unified high-level synthesis framework that uses numerical precision analysis to drive creation of stable mixed-precision custom accelerator hardware with precision-aware resource allocation, along with architecture-aware vectorized code generation for central processing units and graphics processing units. The framework will extend to nondeterministic iterative algorithms that dominate physical AI workloads, enabling development of safe and efficient real-world computing solutions that improve performance and energy efficiency while mitigating catastrophic numerical failure risk.

Performance takes place in Boston, Massachusetts. The award runs through December 31, 2029.

Abstract

The most consequential computing workloads today all face substantial challenges in scaling up computation while delivering energy efficiency, e.g., physical artificial intelligence (AI) workloads such as real-time robot control, large-scale neural network training, power grid management, quantum physics simulation, and other scientific computing. Reducing numerical precision (i.e., using smaller, more concise representations of values) is one of the most effective levers for improving performance and energy efficiency across computing software and hardware, but IT also runs the risk of catastrophic numerical failure. Today, most solutions navigate precision tradeoffs through ad hoc trial-and-error, lacking approaches that can ensure stability. This project addresses this GAP with a cross-layer CO-design framework that leverages two different forms of analysis, numerical precision analysis and control theory, to systematically generate streamlined computer hardware designs and optimized code with provable stability guarantees. Combined, these approaches enable the development of safe and efficient real-world computing solutions. This project takes an interdisciplinary approach, systematically interfacing numerical analysis and control theory with high-performance accelerator hardware-software CO-design to establish a mixed-precision design framework that delivers both stability and performance. This project will: (1) design a unified high-level synthesis framework that uses numerical precision analysis to drive the creation of stable mixed-precision custom accelerator hardware with precision-aware resource allocation for hardware synthesis, as well as architecture-aware vectorized code generation for central processing units (CPU) and graphics processing units (GPU); (2) extend the framework to the nondeterministic, iterative algorithms that dominate physical AI workloads whose convergence behavior cannot be captured by static precision analysis alone but are well characterized by contraction analysis and noise-budget reasoning; and (3) make this framework practical at scale by accelerating the underlying analysis infrastructure through GPU-parallelized interval arithmetic, modular analysis, and code generation. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the foundation's intellectual merit and broader impacts review criteria.- subawards are not planned for this award.