DARPA-BAA-11-45_E-PHI_Amendment 01_Final For Posting_24 May 11.pdf

Broad Agency Announcement

Electronic-Photonic Heterogeneous Integration (E-PHI)

DARPA MTO

DARPA-BAA-11-45

April 14, 2011

Amendment 01 (As amended through May 24, 2011)

Table of Contents:

Part I: Overview Information

Part II: Full Text of Announcement

Sec. I: FUNDING OPPORTUNITY DESCRIPTION

Sec. II: AWARD INFORMATION

Sec. III: ELIGIBILITY INFORMATION

A. Eligible Applicants

B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and Organizational Conflicts of Interest

C. Cost Sharing/Matching

Sec. IV: APPLICATION AND SUBMISSION INFORMATION

A. Address to Request Application Package

B. Content and Form of Application Submission

Sec. V: APPLICATION REVIEW INFORMATION

A. Evaluation Criteria

B. Review and Selection Process

Sec. VI: AWARD ADMINISTRATION INFORMATION

A. Selection Notices

B. Administrative and National Policy Requirements

C. Reporting

D. Electronic Systems

Sec. VII: AGENCY CONTACTS

Sec. VIII: OTHER INFORMATION

A. Intellectual Property Procurement Contract Proposers

B. Non-Procurement Contract Proposers – Noncommercial and Commercial Items (Technical Data and Computer Software)

C. All Proposers – Patents

D. All Proposers – Intellectual Property Representations

E. Other Transactions (OTs)

F. Proposer’s Day

Part I: Overview Information

Federal Agency Name – Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO) Funding Opportunity Title – Electronic-Photonic Heterogeneous Integration (E-

PHI)

Announcement Type – Amendment 01 Funding Opportunity Number – DARPA-BAA-11-45 Catalog of Federal Domestic Assistance Numbers (CFDA) – 12.910 Research and

Technology Development Dates o Posting Date: April 14, 2011 o Proposal Due Date: June 10, 2011 @ 12:00 PM (noon) Eastern Time o Proposer’s Day: May 2, 2011

Concise Description of the Funding Opportunity:

The goal of E-PHI is to develop the necessary technologies, architectures, and design innovations to enable novel chip-scale electronic-photonic/mixed-signal integrated circuits on a common silicon substrate.

Anticipated Individual Awards – Multiple awards are anticipated.

Anticipated Funding Type – 6.1 and 6.2 funds. It is anticipated that awards for both

Fundamental and Non-Fundamental Research may be made as a result of this BAA.

Types of Instruments That May Be Awarded -- Procurement contract, grant, cooperative agreement or other transaction.

Cost Sharing Requirements - None Agency contact o Dr. Scott Rodgers The BAA Coordinator for this effort can be reached at electronic mail: DARPA- BAA-11-45@darpa.mil.

DARPA/MTO

ATTN: DARPA-BAA-11-45

3701 North Fairfax Drive Arlington, VA 22203-1714

PROPOSERS ARE CAUTIONED THAT EVALUATION RATINGS MAY BE LOWERED

AND/OR PROPOSALS REJECTED IF PROPOSAL PREPARATION (PROPOSAL FORMAT,

CONTENT, ETC.) AND/OR SUBMITTAL INSTRUCTIONS ARE NOT FOLLOWED.

THOSE INTENDING TO SUBMIT A PROPOSAL FOR AN ASSISTANCE INSTRUMENT

(GRANT OR COOPERATIVE AGREEMENT) ARE STRONGLY ENCOURAGED TO READ

THE INSTRUCTIONS PROVIDED AT SECTION IV(B)(4) REGARDING THE TIME

REQUIRED TO RECEIVE VALIDATION OF SUBMISSIONS MADE THROUGH

GRANTS.GOV. PROPOSALS THAT ARE VALIDATED AFTER THE PROPOSAL DUE

DATE/TIME WILL BE CONSIDERED LATE AND, AS SUCH, WILL NOT BE REVIEWED.

Part II: Full Text of Announcement

Sec. I: FUNDING OPPORTUNITY DESCRIPTION

The Defense Advanced Research Projects Agency often selects its research efforts through the Broad Agency Announcement (BAA) process. The BAA will appear first on the FedBizOpps website, http://www.fbo.gov/, and Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA.

DARPA is soliciting innovative research proposals in the area of Electronic-Photonic Heterogeneous Integration (E-PHI), an element of the DARPA Diverse Accessible Heterogeneous Integration (DAHI) program (DAHI program managed by Dr. Sanjay Raman).

The DAHI program seeks to develop a manufacturable technology for device-level heterogeneous integration of a wide array of materials and devices (including electronics, photonics, and MEMS technologies) with complex silicon-enabled architectures on a common Si substrate platform. The goal of E-PHI is to develop the necessary technologies, architectures, and design innovations to enable novel chip-scale electronic-photonic/mixed-signal integrated circuits on a common silicon substrate. This technology is expected to enable a wide range of novel chip-scale optoelectronic microsystems, including transceivers for telecommunications, coherent optical systems for sensing (LADAR) and communications, optical arbitrary waveform generators, and multi-wavelength imagers with integrated image processing and readout circuitry. To validate the feasibility and viability of diverse heterogeneous integration technology, E-PHI will seek to demonstrate novel high-performance heterogeneous electronic-photonic integrated microsystems which offer a considerable performance improvement and size reduction versus current, state-of-the-art technologies. Of particular interest are low noise, electronic-photonic signal sources in the radio-frequency (20 GHz) and near infrared (1000- 2000 nm) optical frequency regimes. It is anticipated that such chip-scale, heterogeneously integrated, low noise signal sources will provide unprecedented capabilities for optical gyroscopes, direction finding, optical communications, and frequency references/system synchronization for advanced high-bandwidth RF and mixed signal chip-integrated systems, among other applications. Ultimately, it is expected that the heterogeneous integration technologies developed within E-PHI will be transferrable to a standardized foundry environment and utilize existing Si CMOS fabrication infrastructure.

Background DARPA has an established track record of fostering groundbreaking research in integrated photonics. For instance, the DARPA Data in the Optical Domain – Network (DOD-N) and Electronic and Photonic Integrated Circuits (EPIC) programs have demonstrated some of the most complex photonic integrated circuits (PICs) ever achieved1,2. DARPA has also supported monolithic integration of electronic and photonic devices. For instance, the EPIC program pioneered the development of high performance CMOS-compatible Si nanophotonic devices, such as silicon modulators3 and germanium photodetectors4.

DARPA also has an established record in driving groundbreaking research in heterogeneous integration. For instance, the DARPA COmpound Semiconductor Materials On Silicon (COSMOS) program5 focuses on developing device-level heterogeneous integration technologies to intimately combine advanced compound semiconductor (CS) transistors with high-density silicon circuits. COSMOS has demonstrated that device-level heterogeneous integration of III- V materials on a silicon platform at micrometer length scales is feasible and can yield advanced benefits in mixed-signal microsystem performance. Additionally, recent DARPA-funded research6 has shown the feasibility and potential of heterogeneous photonic integrated circuits on silicon platforms.

E-PHI seeks to build on these successes by developing a heterogeneous integration technology platform to enable optoelectronic/mixed-signal integrated circuits which utilize an optimal combination of photonic and optoelectronic devices integrated on a Si substrate platform with Si CMOS (or BiCMOS) circuits. Examples of potential heterogeneous integration approaches include micro-assembly, epitaxial layer bonding and printing, and direct epitaxial growth within silicon-based process flows (note that this listing of examples in no way limits the heterogeneous integration approaches that may be proposed to this BAA).

State of the Art Signal Sources and Future Potential:

While mature, low-noise optical oscillator signal sources exist, such as fiber, external-cavity, quantum-dot, and mode-locked lasers, ultra-low-noise performance comes at the cost of increased device size. The large size originates from the mechanical and thermal noise suppression methods used to stabilize the high-Q cavity needed to produce low noise sources.

As an example, monolithic semiconductor lasers are efficient, compact sources that typically

1 S.C. Nicholes, et al., “The world’s first InP 8x8 monolithic tunable optical router (MOTOR) operating at 40Gbps line rate per port”, 2009 Conference on Optical Fiber Communication – OFC 2009, pp. 1-3 (2009).

2 Huang, A., et al., "A 10Gb/s photonic modulator and WDM MUX/DEMUX integrated with electronics in 0.13µm SOI CMOS," Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, pp.922-929 (2006).

3 Xu, Qianfan, et al.; “Micrometre-scale silicon electro-optic modulator.” Nature, 435, 7040, p. 325-7 (2005).

4 D. Ahn, et al., "High performance, waveguide integrated Ge photodetectors," Opt. Express 15, 3916-3921 (2007).

5 Raman, S., et al., "The DARPA COSMOS program: The convergence of InP and Silicon CMOS technologies for high-performance mixed-signal," Proceedings of 2010 International Conference on Indium Phosphide & Related Materials (IPRM), p. PL2.

6 A. Fang, H. Park, O. Cohen, R. Jones, M. Paniccia, and J. Bowers, "Electrically pumped hybrid AlGaInAs-silicon evanescent laser," Opt. Express 14, 9203-9210 (2006).

have large linewidth enhancement factors and relatively low Q, resulting in noisy oscillator performance. The total noise of such oscillators can be greatly reduced using off-chip solutions such as external optical cavities, frequency references, and electronic feedback mechanisms (as depicted in Figure 1(a)). For these low noise semiconductor sources however, the size of these feedback mechanisms dominates the total package size, negating the size benefit of using a semiconductor laser and making chip-scale integration impossible. Integration of all optical oscillator components on a single chip can lead to dramatic size reduction for the overall system.

(a)

(b)

Figure 1: (a) Example block diagram of frequency-stabilized laser source (b) Example block diagram of an optoelectronic oscillator

In addition to size reduction, the use of chip-scale integrated photonics and electronics on silicon has the potential for enabling substantial performance gains over state-of-the-art compact optical oscillators. Some of the expected benefits include higher-speed electronic feedback, enhanced coupling among photonic components, and additional flexibility in utilizing nonlinear optical phenomena, and better thermal and vibration tolerance. Recent advances show great progress in the development of needed components including: high-Q cavities, low-loss waveguides, Laser Modulator

Photo-detector

Integrated Optical

Delay Line

Electronic Filter

Optical Out

Phase shifter

RF Out RF Amplifier

Photonic Interconnects

Electrical Interconnects Legend:

Δt

Laser

Optical Isolator

Optical Filter

Coupler

Optical Out

Reference Signal

Loop Filter

Error Signal

Correction Signal

Photo-detectors integrated frequency references, low linewidth enhancement factor semiconductor materials, and nonlinear mixing elements. Opto-electronic oscillators (OEO), an example of which is depicted in Figure 1(b), have also demonstrated that these advances in photonics can be utilized to produce extremely pure RF tones, and it is expected that the heterogeneous integration of the optical and electronic components will push such circuits to new levels of performance.

Technical Areas:

The objective of E-PHI is to develop novel electronic-photonic integrated circuit technologies which can be integrated with Si CMOS electronics and other microsystems components on a common silicon-based substrate platform. The challenges associated with this goal will be addressed in three technical areas: (I) Heterogeneous Electronic-Photonic Integration Process and Device Technologies, (II) Heterogeneously Integrated Electronic-Photonic Architectures, and (III) Demonstration Microsystems. Proposals to individual technical areas within this BAA will be considered; however, proposals that comprehensively address all technical areas are of particular interest.

Technical Area I: Heterogeneous Electronic-Photonic Integration Process and Device Technologies The goal of this technical area is to develop the fabrication and device technologies needed to heterogeneously integrate different photonic/optoelectronic materials and devices at the device scale on a Si CMOS-compatible substrate platform. Of particular interest are fabrication approaches that can be developed in a modular way, such that individual process modules can be added or removed from a heterogeneously integrated circuit process flow depending upon the material and device needs of the circuit. It is envisioned that these process modules can ultimately be transferred as needed to a foundry manufacturing process flow for heterogeneously integrated circuits. Therefore, such process modules should be compatible with deep sub-micron Si CMOS (in terms of thermal budget, process contamination, etc.), as well as with each other.

Consequently, proposals that outline a path to high yield and manufacturability and can be implemented using standard microelectronics infrastructure with as few modifications as possible are of particular interest. Also of interest is the development of accurate heterogeneously integrated modeling techniques and device models (suitable for interfacing with standard integrated circuit design tools). Such models are necessary to facilitate the inclusion of new process modules in process design kits for use in future electronic-photonic integrated circuit design. In addition, close interaction with the architectural simulation tasks of Technical Area II is strongly encouraged to increase the accuracy of architecture simulations as the program progresses.

Approaches that develop the fabrication and device technology needed for the Technical Area III demonstration circuits are of particular interest. The following is a non-exhaustive list of device and material technologies that are of interest in this technical area: high-Q cavities, low-loss waveguides, integrated frequency references, low linewidth enhancement factor semiconductor materials, integrated optical isolators, and nonlinear mixing elements. For those proposing to this technical area only, proposers should illustrate how their advances are relevant to the demonstration circuits discussed in Technical Area III. In all cases, the proposed work should demonstrate integration of these components at the device-scale on a common Si substrate platform. Of particular interest are approaches that demonstrate device-level integration of their technology with advanced silicon CMOS devices, especially those that employ control electronics on a common Si substrate platform with photonic device(s) for optimization of photonic device performance.

Technical Area II: Heterogeneously Integrated Electronic-Photonic Architectures This Technical Area focuses on developing novel architectures and design methodologies that take advantage of heterogeneously integrated materials and electronic and photonic devices. The current state of the art in photonic integrated circuits has primarily been established with materials and devices that are native to the underlying substrate technology (typically InP for PICs utilizing photonic gain or Si for PICs utilizing CMOS manufacturing infrastructure).

However, E-PHI will significantly expand the electronic-photonic integrated circuit design space in terms of materials and devices. Thus, novel concepts and architectures will be needed to take maximum advantage of this new heterogeneous design space.

To provide focus for this technical area, preference will be given to approaches that develop the design concepts and architectures needed for the Technical Area III demonstration circuits. It is expected that these design concepts may employ Si and/or III-V photonic devices (including active and passive devices), Si CMOS transistors, and/or III-V high-speed transistors. It is envisioned that design innovations can enable heterogeneously integrated electronic-photonic integrated circuits to greatly surpass the performance of equivalent hybrid discrete-component electronic-photonic systems in many respects. For instance, in the case of electronic-photonic signal sources, the compact integration of multiple components will likely provide enhanced coupling to high-Q cavities and diminish relative motion between components, thereby reducing the system’s susceptibility to vibration. For pulsed optical sources and opto-electronic oscillators, reducing the device size can remove supermodes from high-frequency cavities, lowering the pulse-to-pulse jitter and oscillator phase noise. Finally, the integration of optical sources with compact waveguides allows for novel uses of nonlinear phenomena and wave mixing to remove noise and produce cavity-free, low-noise oscillators.

One key challenge in this Technical Area concerns the development of innovative designs and architectures for environmental stability in heterogeneously integrated circuits. For instance, these circuits present unique thermal management challenges due to the presence of multiple device layers; it is expected that innovative designs and architectures can greatly facilitate thermal management in these circuits. Innovative design concepts that mitigate sensitivity to other environmental variables (such as temperature cycling, vibration, etc.) are also of interest in this Technical Area.

Expected deliverables for this Technical Area include detailed device-level simulations and tradeoff studies of heterogeneously integrated architectures using commercially available simulation tools. In addition, close interaction with the device modeling task of Technical Area I is strongly encouraged to increase the accuracy of architecture simulations as the program progresses. Fabrication of these architectures is not sought within this Technical Area.

Technical Area III: Demonstration Microsystems The goal of this technical area is the demonstration of heterogeneously integrated microsystems (such as low-noise RF and optical signal sources) and associated control circuitry fully integrated on a single silicon substrate. Of particular interest are low noise, electronic-photonic signal sources in the radio-frequency (20GHz) and near infrared (1000-2000nm) optical frequency regimes. Proposals are encouraged to select one of the following demonstration microsystems:

(A) low-noise, low-jitter laser sources, (B) low-noise, RF optoelectronic signal sources, and (C) other advanced electronic-photonic integrated circuit demonstrators. For demonstrations A and B, tunability of the signal frequency is not required. However, proposals which demonstrate a system capable of reconfiguration or frequency tuning without negatively impacting the primary performance metrics are of particular interest. Proposals should also address the manufacturability and cost when fabricated in a production environment, as well as the potential to integrate the signal source with other heterogeneously integrated circuits on a common Si substrate platform. The end-of-program goal must result in a courier-survivable device suitable for packaging to be delivered to the government for testing and demonstration to technology adopters. Demonstration devices should also be able to operate under nominal room temperature conditions (see metrics table for details).

Demonstration A: Laser Sources This demonstration focuses on demonstrating stabilized laser sources that exploit heterogeneous integration technology for advanced performance. For this demonstration, proposers are encouraged to select either a continuous-wave or pulsed laser source, as described below.

Demonstration A.1: Continuous Wave Laser Sources This demonstration will focus on producing a low-noise source in the near infrared (1000-2000

nm) that can operate in continuous-wave mode. Current low-noise continuous-wave lasers include ultra-stable fiber lasers with frequency noise7 levels of 1600 Hz2/Hz at an offset of 1 kHz from the carrier frequency, while typical semiconductor-based solutions have noise levels over

7 The frequency noise power spectrum density, S(f), is related to the phase noise power spectrum density, S(f), via S(f)=f2 S(f). The commonly reported single-sideband phase noise power spectrum density is (f)= S(f)/2.

one hundred times larger. The objectives of this demonstration are to provide fiber laser-like frequency noise in a chip-based system without sacrificing output power. Primary applications include Doppler LADAR sources, navigation, and coherent communications.

Demonstration A.2: Pulsed Laser Sources This demonstration will focus on producing low-jitter, pulsed laser sources with repetition rates of 20 GHz which do not require synchronization with an external clock. The wavelength area of interest is in the near infrared (1000-2000 nm). Current large, external-cavity, passively mode-locked, fiber ring lasers have demonstrated absolute jitter of 29 fs (10 Hz – 3 MHz) with monolithic semiconductor-based solutions demonstrating jitter as low as 122 fs (4-80 MHz).

The goal of this demonstration is to develop sources with the ultra-low jitter of external cavity approaches, but in the much smaller size offered by heterogeneous integration technology.

Applications include the production of frequency combs, ranging, vibrometry, photonic analog to digital conversion, and precision synchronization over long distances. The objectives focus on low jitter and peak output power.

Demonstration B: RF Opto-Electronic Signal Sources This demonstration focuses on developing an RF oscillator possessing appreciable RF output power and low-phase noise in a chip-integrated form-factor. Frequency comb and fiber-based opto-electronic signal sources have demonstrated impressive close-to-the-carrier and far-from-the-carrier phase noise levels, respectively. Additional advantages of photonic-based oscillators include high cavity quality factors (Qs of 1010 have been demonstrated) and low oscillator acceleration sensitivities (better than 10-10/g has been demonstrated). Primary applications include Doppler and synthetic aperture RADAR, time-keeping, ultra-wideband data conversion and communications.

Demonstration C: Other Advanced Electronic-Photonic Integrated Circuit Demonstrators Proposals for other novel demonstration systems beyond those listed above (as defined by the proposers) that utilize the capabilities of heterogeneously integrated electronic-photonic integrated circuits in a capability- or performance-enhancing way will also be considered. Those proposing this demonstration are encouraged to provide background and justification that their proposed demonstration meets or exceeds Demonstrations A and B in terms of scientific and technical merit and relevance to the goals of E-PHI as well as DARPA and the DoD.

Program Organization:

Proposers are encouraged to specify intermediate goals/metrics and establish a schedule of deliverables consistent with the final program objectives. In addition to the program goals outlined in this BAA, proposers are also encouraged to propose additional performance metrics as appropriate for their particular approach or application. Performance will be continually evaluated based on technical progress toward the proposer-defined intermediate goals/metrics and the likelihood that progress will lead to achievement of the final goals of each technical area.

Performance Goals:

Technical Area I Goals:

The quantitative end-of-program goals for this technical area are described below. Proposals that meet or exceed the end-of-program goals are of particular interest. Proposals should specify intermediate goals for each metric as part of the proposed program plan. Proposals should also supplement the metrics given below with any additional metrics which they deem to be appropriate to gauging the overall performance of their specific process or device technology.

Heterogeneous Electronic-Photonic Integration Process and Device Technologies Metric

Goal

Heterogeneous optical insertion loss* (dB) Performer-specified

Heterogeneously integrated device performance** (%) > 90

Si CMOS Performance*** (%) > 90

* The total coupling loss that results from heterogeneous integration of a photonic device with a CMOS-compatible optical waveguide. This value should include coupling loss both into and out of the heterogeneously integrated device (for devices with optical inputs as well as outputs). It is the responsibility of the proposers to propose and justify appropriate quantitative metrics for the proposed device type.

** The ratio of the performance of heterogeneously integrated devices to that of the same devices fabricated by the same process on a native substrate. It is the responsibility of the proposers to propose and justify appropriate device metrics to gauge the overall performance of the heterogeneously integrated devices. It is expected that, in some cases, it will be appropriate to include more than one metric per device type for this purpose.

*** The ratio of each of the following performance metrics of Si CMOS transistors subsequent to heterogeneous integration to that of equivalent Si CMOS transistors fabricated in their native process without heterogeneous integration: transconductance, on/off ratio, inverter delay. Note that this goal only applies to efforts which integrate Si CMOS devices with heterogeneously integrated photonic/optoelectronic devices.

Technical Area II Goals:

Proposals should include clear quantitative end-of-program goals for their proposed work under this technical area. Of particular interest are proposals that map their goals directly to the goals of Technical Area III and explain how their design concepts can enable the Technical Area III demonstration microsystems. Proposals should specify intermediate goals for each metric as part of the proposed program plan.

Expected deliverables for this Technical Area include detailed device-level simulations and tradeoff studies of heterogeneously integrated architectures using commercially available simulation tools. Fabrication of these architectures is not sought within this Technical Area.

Technical Area III Goals:

The quantitative end-of-program goals for this technical area are described below. Proposals that meet or exceed the end-of-program goals are of particular interest. Proposals should specify intermediate goals for each metric as part of the proposed program plan.

Demonstration A: Laser Sources The tables below outline the quantitative goals for continuous-wave and pulsed laser sources in Demonstration A:

Demonstration A.1: Continuous-Wave Laser Source

CW Laser Metric Program Goal

Wavelength* (nm) 1000 - 2000

Output Power (mW) > 20

RIN (dB/Hz) @ 10 kHz < -165

SMSR (dBc) < -80

Frequency Noise

Offset Frequency Sf (Hz2/Hz)

100 Hz < 100

1 kHz < 10

> 10 kHz < 1

Heat Sink Temperature Limit (oC)** > 25

Substrate Area (cm2) < 10

* The wavelength does not need to be tunable but must lie within the given bounds.

**The lowest allowable temperature at the heat sink-die interface.

Demonstration A.2: Pulsed Laser Source

Pulsed Laser Metric Program Goal

Wavelength (nm) 1000 - 2000

Peak Power (mW) > 200

Rep. Rate (GHz) = 20

RMS Amplitude Variation (%)* < 0.08

Absolute Jitter (fs)* < 10

Heat Sink Temperature Limit (oC)** > 25

Substrate Area (cm2) < 10

* RMS amplitude variation and jitter must be integrated 1 Hz to 10 GHz.

Demonstration B: RF Opto-electronic Signal Source

Opto-Electronic Oscillator Metric

Program Goal

Output RF Frequency 20 GHz

Phase Noise*

Offset Frequency (Hz) Phase Noise (dBc/Hz)

1 -104

10 -124

100 -144

1000 -161

10000 -161

RF Output Power > 20 mW

DC Power Consumption < 20 W

Heat Sink Temperature Limit (oC)**

> 25

Substrate Area < 10 cm2

* This phase noise profile corresponds to an integrated jitter of 10fsec (1Hz - 10GHz)

Demonstration C: Other Advanced Electronic-Photonic Integrated Circuit Demonstrators Proposals should set clear quantitative end-of-program goals for their proposed work and should also specify intermediate goals for each metric as part of the proposed program plan. Of particular interest are proposals that utilize the capabilities of heterogeneously integrated electronic-photonic integrated circuits in an advanced way, comparably to Demonstrations A and B. Proposals in this technical area are expected to conform to the substrate area and heat sink temperature limit goals specified for Demonstrations A and B.

Characterization and Validation:

In Technical Areas I and III, government characterization and evaluation is expected. At the end of the effort a single, courier-survivable microsystem shall be shipped to a government facility for validation and permanent archiving. The microsystem will be tested to validate performance using well established methods such as single side-band phase noise (f) = ½ Sφ(f), Allan Deviation σy(t), and RIN spectra (see IEEE Std. 1139-1999), or other methods as appropriate for the microsystem under test. Furthermore, measurement of microsystem performance in operationally relevant environmental conditions such as varying temperatures, platform vibration, warm-up time, and electromagnetic interference, will be considered to help establish possible insertion opportunities.

Technology Transition Plan:

Proposals should include a technology transition plan that addresses how the E-PHI signal sources as well as the heterogeneous integration processes will be transitioned to enhance DoD capabilities. Successful transition plans will support the DAHI program vision of establishing a robust foundry capability consisting of multiple diverse heterogeneous integration technologies combined with Si CMOS. This foundry capability is envisioned to be made available to a broad community of DoD microsystems designers. Additionally, proposals should also outline plans for transition of the E-PHI signal sources as standalone components.

Sec. II: AWARD INFORMATION

Multiple awards are anticipated. The amount of resources made available under this BAA will depend on the quality of the proposals received and the availability of funds.

The Government reserves the right to select for negotiation all, some, one, or none of the proposals received in response to this solicitation, and to make awards without discussions with proposers. The Government also reserves the right to conduct discussions if it is later determined to be necessary. If warranted, portions of resulting awards may be segregated into pre-priced options. Additionally, DARPA reserves the right to accept proposals in their entirety or to select only portions of proposals for award. In the event that DARPA desires to award only portions of a proposal, negotiations may be opened with that proposer. The Government reserves the right to fund proposals in phases with options for continued work at the end of one or more of the phases.

Awards under this BAA will be made to proposers on the basis of the evaluation criteria listed below (see section labeled “Application Review Information”, Sec. V.), and program balance to provide overall value to the Government. Proposals identified for negotiation may result in a procurement contract, grant, cooperative agreement, or other transaction depending upon the nature of the work proposed, the required degree of interaction between parties, and other factors. The Government reserves the right to request any additional, necessary documentation once it makes the award instrument determination. Such additional information may include but is not limited to Representations and Certifications. The Government reserves the right to remove proposers from award consideration should the parties fail to reach agreement on award terms, conditions and cost/price within a reasonable time or the proposer fails to timely provide requested additional information.

As of the date of publication of this BAA, DARPA expects that program goals for this BAA may be met by proposers intending to perform 'fundamental research,' i.e., basic or applied research performed on campus in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization the results of which ordinarily are restricted for proprietary or national security reasons. Notwithstanding this statement of expectation, DARPA is not prohibited from considering and selecting research proposals that, while perhaps not qualifying as 'fundamental research' under the foregoing definition, still meet the BAA criteria for submissions. If proposals are selected for award that offer other than a fundamental research solution, then DARPA will either work with the proposer to modify the proposed statement of work to bring the research back into line with fundamental research or else the proposer will agree to restrictions in order to receive an award.

See Section VI.B.4 for further information on fundamental, non-fundamental and restricted research. In all cases, the DARPA contracting officer shall have sole discretion to select award instrument type and to negotiate all instrument provisions with selectees.

Sec. III: ELIGIBILITY INFORMATION

A. Eligible Applicants

All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA. Historically Black Colleges and Universities (HBCUs), Small Businesses, Small Disadvantaged Businesses and Minority Institutions (MIs) are encouraged to submit proposals and join others in submitting proposals; however, no portion of this announcement will be set aside for these organizations’ participation due to the impracticality of reserving discrete or severable areas of this research for exclusive competition among these entities.

Federally Funded Research and Development Centers (FFRDCs) and Government entities (Government/National laboratories, military educational institutions, etc.) are subject to applicable direct competition limitations and cannot propose to this BAA in any capacity unless they address the following conditions. FFRDCs must clearly demonstrate that the proposed work is not otherwise available from the private sector AND must also provide a letter on letterhead from their sponsoring organization citing the specific authority establishing their eligibility to propose to government solicitations and compete with industry, and compliance with the associated FFRDC sponsor agreement and terms and conditions. This information is required for FFRDCs proposing to be prime or subcontractors. Government entities must clearly demonstrate that the work is not otherwise available from the private sector and provide written documentation citing the specific statutory authority (as well as, where relevant, contractual authority) establishing their ability to propose to Government solicitations. At the present time, DARPA does not consider 15 U.S.C. 3710a to be sufficient legal authority to show eligibility.

While 10 U.S.C. 2539b may be the appropriate statutory starting point for some entities, specific supporting regulatory guidance, together with evidence of agency approval, will still be required to fully establish eligibility. DARPA will consider eligibility submissions on a case-by-case basis; however, the burden to prove eligibility for all team members rests solely with the Proposer.

B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and

Organizational Conflicts of Interest

Current federal employees are prohibited from participating in particular matters involving conflicting financial, employment, and representational interests (18 USC 203, 205, and 208.).

The DARPA Program Manager for this BAA is Dr. Scott Rodgers. Once the proposals have been received, and prior to the start of proposal evaluations, the Government will assess potential conflicts of interest and will promptly notify the proposer if any appear to exist. (Please note the Government assessment does NOT affect, offset, or mitigate the proposer’s own duty to give full notice and planned mitigation for all potential organizational conflicts, as discussed below.)

Without prior approval or a waiver from the DARPA Director, in accordance with FAR 9.503, a Contractor cannot simultaneously provide scientific, engineering, technical assistance (SETA) or similar support and also be a technical performer. Therefore, all Proposers as well as proposed subcontractors and consultants must affirm whether they (their organizations and individual team members) are providing SETA or similar support to any DARPA technical office(s) through an active contract or subcontract. All affirmations must state which office(s) the Proposer, subcontractor, consultant, or individual supports and identify the prime contract number(s).

Affirmations shall be furnished at the time of proposal submission. All facts relevant to the existence or potential existence of organizational conflicts of interest (FAR 9.5) must be disclosed. The disclosure must include a description of the action the Proposer has taken or proposes to take to avoid, neutralize, or mitigate such conflict. If in the sole opinion of the Government after full consideration of the circumstances, a proposal fails to fully disclose potential conflicts of interest and/or any identified conflict situation cannot be effectively mitigated, the proposal will be rejected without technical evaluation and withdrawn from further consideration for award.

If a prospective Proposer believes that any conflict of interest exists or may exist (whether organizational or otherwise) or has questions on what constitutes a conflict of interest, the Proposer should promptly raise the issue with DARPA by sending his/her contact information and a summary of the potential conflict to the BAA mailbox before time and effort are expended in preparing a proposal and mitigation plan

C. Cost Sharing/Matching

Cost sharing is not required for this particular program; however, cost sharing will be carefully considered where there is an applicable statutory condition relating to the selected funding instrument (e.g., for any Other Transactions under the authority of 10 U.S.C. § 2371). Cost sharing is encouraged where there is a reasonable probability of a potential commercial application related to the proposed research and development effort.

Sec. IV: APPLICATION AND SUBMISSION INFORMATION

A. Address to Request Application Package

This solicitation contains all information required to submit a proposal. No additional forms, kits, or other materials are needed. This notice constitutes the total BAA. No additional information is available, nor will a formal Request for Proposal (RFP) or additional solicitation regarding this announcement be issued. Requests for same will be disregarded.

B. Content and Form of Application Submission

1. Security and Proprietary Issues

The Government anticipates proposals submitted under this BAA will be unclassified. However, if a proposal is submitted as “Classified National Security Information” as defined by Executive Order 13526, as amended, then the information must be marked and protected as though classified at the appropriate classification level and then submitted to DARPA for a final classification determination.

Security classification guidance via a DD Form 254, “DoD Contract Security Classification Specification,” will not be provided at this time, since DARPA is soliciting ideas only. After reviewing the incoming proposals, if a determination is made that the award instrument may result in access to classified information, a DD Form 254 will be issued and attached as part of the award.

Proposers choosing to submit a classified proposal from other classified sources must first receive permission from the respective Original Classification Authority in order to use their information in replying to this BAA. Applicable classification guide(s) should also be submitted to ensure the proposal is protected at the appropriate classification level.

Classified submissions shall be appropriately and conspicuously marked with the proposed classification level and declassification date. Submissions requiring DARPA to make a final classification determination shall be marked as follows:

CLASSIFICATION DETERMINATION PENDING. Protect as though classified (insert the recommended classification level: (e.g., Top Secret, Secret or Confidential)

Classified submissions shall be in accordance with the following guidance:

Confidential and Secret Collateral Information: Use classification and marking guidance provided by previously issued security classification guides, the Information Security Regulation (DoD 5200.1-R), and the National Industrial Security Program Operating Manual (DoD 5220.22-M) when marking and transmitting information previously classified by another Original Classification Authority. Classified information at the Confidential and Secret level may be submitted via ONE of the two following methods:

1. Hand-carried by an appropriately cleared and authorized courier to the DARPA CDR. Prior to traveling, the courier shall contact the DARPA CDR at 571-218-4842 to coordinate arrival and delivery.

OR

2. Mailed via appropriate U.S. Postal Service methods (e.g., (USPS)

Registered Mail or USPS Express Mail). All classified information will be enclosed in opaque inner and outer covers and double wrapped. The inner envelope shall be sealed and plainly marked with the assigned classification and addresses of both sender and addressee.

The inner envelope shall be addressed to:

Defense Advanced Research Projects Agency

ATTN: MTO

Reference: DARPA-BAA-11-45

The outer envelope shall be sealed with no identification as to the classification of its contents and addressed to:

Defense Advanced Research Projects Agency Security & Intelligence Directorate, Attn: CDR

All Top Secret materials: Top Secret information should be hand carried by an appropriately cleared and authorized courier to the DARPA CDR. Prior to traveling, the courier shall contact the DARPA CDR at 571 218-4842 to coordinate arrival and delivery.

Special Access Program (SAP) Information: SAP information must be transmitted via approved methods. Prior to transmitting SAP information, contact the DARPA SAPCO at 703-526-4052 for instructions.

Sensitive Compartmented Information (SCI): SCI must be transmitted via approved methods. Prior to transmitting SCI, contact the DARPA Special Security Office (SSO) at 703- 248-7213 for instructions.

Proprietary Data: All proposals containing proprietary data should have the cover page and each page containing proprietary data clearly marked as containing proprietary data. It is the Proposer’s responsibility to clearly define to the Government what is considered proprietary data.

Proposers must have existing and in-place prior to execution of an award, approved capabilities (personnel and facilities) to perform research and development at the classification level they propose. It is the policy of DARPA to treat all proposals as competitive information, and to disclose their contents only for the purpose of evaluation. Proposals will not be returned. The original of each proposal received will be retained at DARPA and all other non-required copies destroyed. A certification of destruction may be requested, provided the formal request is received at this office within 5 days after unsuccessful notification.

2. Proposal Submission Information

Proposers are required to submit full proposals by the time and date specified in the BAA in order to be considered during the single round of selections. Proposals received after the time and date specified in the BAA will be considered late and as such, will not be evaluated.

The typical proposal should express a consolidated effort in support of one or more related technical concepts or ideas. Disjointed efforts should not be included into a single proposal.

Restrictive notices notwithstanding, proposals may be handled, for administrative purposes only, by a support contractor. This support contractor is prohibited from competition in DARPA technical research and is bound by appropriate nondisclosure requirements. Proposals and proposal abstracts may not be submitted by fax or e-mail; any so sent will be disregarded.

Proposals not meeting the format described in the BAA may not be reviewed.

For Proposers Requesting an Assistance Instrument:

Grant or cooperative agreement proposals may only be submitted to DARPA through Grants.gov (using the APPLY function) or in hard-copy. Grant or cooperative agreement proposals may not be submitted through any other means (including T-FIMS and other comparable systems). If proposers intend to use Grants.gov as their means of submission, then they must submit their entire proposal through Grants.gov; applications cannot be submitted in part to Grants.gov and in part as a hard-copy. Proposers using the Grants.gov APPLY do not submit paper proposals in addition to the Grants.gov APPLY electronic submission.

Proposers must complete the following steps before submitting proposals on Grants.gov (these steps are also detailed at www.grants.gov/applicants/get_registered.jsp):

Proposers must obtain a DUNS number Proposers must register their organization in the Central Contractor Registration (CCR)

(https://www.bpn.gov/ccr/default.aspx ) Proposers must register the Authorized Organization Representative (AOR) in Grants.gov Proposers must have the organization’s E-BIZ point of contact authorize the AOR to submit applications.

Once Grants.gov has received a proposal submission, Grants.gov will send two email messages to advise proposers as to whether or not their proposals have been validated or rejected by the system; IT MAY TAKE UP TO TWO DAYS TO RECEIVE THESE EMAILS. The first email will confirm receipt of the proposal by the Grants.gov system; this email only confirms receipt, not acceptance, of the proposal. The second will indicate that the application has been successfully validated by the system prior to transmission to the grantor agency or has been rejected due to errors. If the proposal is validated, then the proposer has successfully submitted their proposal. If the proposal is rejected, the proposer will have to resubmit their proposal.

Once the proposal is retrieved by DARPA, the proposer will receive a third email from Grants.gov. To avoid missing deadlines, proposers should submit their proposals in advance of the final proposal due date with sufficient time to receive confirmations and correct any errors in the submission process through Grants.gov. For more information on submitting proposals to Grants.gov, visit the Grants.gov submissions page at:

http://grants.gov/applicants/apply_for_grants.jsp.

Technical support for Grants.gov submissions may be reached at 1-800-518-4726 or support@grants.gov.

Proposers electing to submit grant or cooperative agreement proposals as hard copies must complete the SF 424 R&R form (Application for Federal Assistance, Research and Related) available on the Grants.gov website:

http://www.grants.gov/agencies/aapproved_standard_forms.jsp#2.

If submitting hard-copy, an original and (4) copies of the proposal and (4) electronic copies of the proposal on a CD-ROM shall be submitted to DARPA/MTO, 3701 North Fairfax Drive, Arlington, VA 22203-1714 (Attn: DARPA-BAA-11-45) no later than time and date specified in Section IV, Application and Submission Information

For Proposers Requesting a Contract or Other Transaction Agreement:

Unclassified proposals sent in response to DARPA-BAA-11-45, unless seeking a grant or cooperative agreement, must be submitted through T-FIMS (no email, fax or hardcopy submissions are permitted). See https://www.tfims.darpa.mil/baa/ for more information on how to request an account, upload proposals, and use the T-FIMS tool. Because proposers using T- FIMS may encounter heavy traffic on the web server, and T-FIMS requires a registration and certificate installation for all proposers, proposers should not wait until the day the proposal is due to create an account in T-FIMS and/or submit the proposal. All proposers using T-FIMS must also encrypt the proposal, as per the instructions below.

All proposals submitted electronically by means of an Electronic Business Application Tool or proposal submission web site (not including Grants.gov) must be encrypted using Winzip or PKZip with 256-bit AES encryption. Only one zipped/encrypted file will be accepted per proposal and proposals not zipped/encrypted will be rejected by DARPA. An encryption password form must be completed and emailed to DARPA-BAA-11-45@darpa.mil at the time of proposal submission. See https://www.tfims.darpa.mil/baa/ for the encryption password form for T-FIMS submissions only.

Note the word “PASSWORD” must appear in the subject line of the above email and there are minimum security requirements for establishing the encryption password. Failure to provide the encryption password may result in the proposal not being evaluated. For further information and instructions on how to zip and encrypt proposal files, see https://www.tfims.darpa.mil/baa/ for TFIMS submissions only.

For All Proposers:

All administrative correspondence and questions on this solicitation should be directed to DARPA-BAA-11-45@darpa.mil DARPA intends to use electronic mail for correspondence regarding DARPA BAA-11-45. Proposals may not be submitted by fax or e-mail; any so sent will be disregarded. DARPA encourages use of the Internet for retrieving the BAA and any other related information that may subsequently be provided

3. Full Proposal Format

All full proposals must be in the format given below. Nonconforming proposals may be rejected without review. Proposals shall consist of two volumes. All pages shall be printed on 8-1/2 by 11 inch paper with type not smaller than 12 point. Smaller font may be used for figures, tables and charts.