Attachment A Statement of Work.docx

STATEMENT OF WORK

HBT-based InP Foundry Runs for Transistor Modeling 672.03

I. BACKGROUND INFORMATION

The National Institutes of Standards and Technology’s (NIST’s) High Speed Measurement Group has a requirement for additional sets of integrated circuits to be used in the development of high-frequency transistor models and novel circuits at sub-mmWave frequencies. The extraction of transistor models using NIST on-wafer calibrations fits in the mission of the CHIPS program. These circuits will be modifications of prior NIST design submissions to Teledyne Scientific. They will be based on InP HBT transistors and shall have the capability of producing power amplification from 25GHz up to 650 GHz, mixers, phase-locked loops, dynamic frequency dividers, and oscillators.

The maximum breakdown Voltage Collector-Emitter (VCE) must be equal or higher than 3.5 V. The InP HBT circuits shall have been demonstrated to generate power amplifiers with 0.8 mW of output power at 585 GHz and 20 dB of small signal gain at 650 GHz with no more than 10 stages. The ft of the transistor shall be at least 520 GHz and the fmax of the transistor shall be at least 1.1 THz.

II. SCOPE

The goal of this contract is to provide process design kits (PDKs) and facilitate the design, design review check (DRC), fabrication, and delivery of electronic circuits for 2 InP multi-project wafer (MPW) foundry runs before the end of 9/30/26 to support high-frequency transistor modeling. The size of the tile will be approximately 6 x 6 mm for each design cycle.

The circuits will be based on InP HBT transistors capable of producing power amplifiers with 0.8 mW of output power at 585 GHz and 20 dB of small signal gain at 650 GHz, mixers, phase-locked loops, dynamic frequency dividers, and oscillators. The substrate is semi-insulating InP with a 100 orientation or other suitable electro-optic material and should be polished on the back side to allow electro-optic sampling through the back of the substrate. The back of the substrate should also be clean and suitable for deposition of anti-reflective coatings at NIST. It must be possible to form coplanar waveguide (CPW) transmission lines on the top surface of the substrate and to remove semi-conducting epi layers under the CPW to reduce substrate losses in the CPW. The technology must also support thin-film microstrip transmission lines on the top surface in BCB or similar low-loss low-dielectric-constant insulators suitable for fabricating broadband combiners and other passive microstrip circuitry that operate up to 650 GHz. The conductors on the top surface of the wafer must be robust enough to allow wire bonding, on-wafer probing, and solder connections. New designs resulting from this effort will remain confidential property of NIST.

III. MINIMUM REQUIREMENTS

Line Item 0001: Provide Process Design Kit Description: Contractor will provide a Design Kit consisting of linear transistor models, design rules and layout examples to illustrate the design rules, and an example layout of the existing THz design.

Quantity: 1 Technical Specifications

A. Layouts will be provided in GDS format. Transistor models will be provided in Keysight Advance Design System (ADS) format. Design rules and tips will be provided in PowerPoint format.

B. Contractor will provide design consultation services for NIST personnel in the use of the libraries and provide guidance on amplifier and component design. Contractor will provide consultation for a period of ARO+18 months C. Delivery of Design Kit with design rules and tips: 10 days After Receipt of Order (ARO) Line Item 0002: Design Review and Fabrication #1 Description: Contingent upon delivery of designs from NIST, Contractor will fabricate integrated circuits as designed by NIST with design assistance from Contractor using its standard foundry technology. NIST will provide layouts in GDS format to Contractor.

Quantity: 1 Technical Specifications A. Contractor will clean up designs and perform Layout vs Schematic (LVS) and Design Rule Check (DRC) to ensure NIST designs adhere to the foundry process.

B. Contractor will fabricate and deliver portions of wafers, with the area of the provided wafer determined by sharing of the mask.

C. Delivery: Upon delivery by NIST of the layout to Contractor for a period not to exceed 9 months after receipt of designs. Approximate tapeout date between 04/01/2025 - 09/30/2025.

Line Item 0003: Design Review and Fabrication #2 Description: Contingent upon delivery of designs from NIST, Contractor will fabricate integrated circuits as designed by NIST with design assistance from Contractor using its standard foundry technology. NIST will provide layouts in GDS format to Contractor.

Quantity: 1 Technical Specifications A. Contractor will clean up designs and perform LVS and DRC to ensure NIST designs adhere to the foundry process.

B. Contractor will fabricate and deliver portions of wafers, with the area of the provided wafer determined by sharing of the mask.

C. Delivery: Upon delivery by NIST of the layout to Contractor for a period not to exceed 9 months after receipt of designs. Approximate tapeout date between 06/01/2026 - 11/30/2026.

IV. DELIVERABLES/PERIOD OF PERFOMRANCE/LEAD TIME

V. PLACE OF PERFORMANCE

All work shall be performed at contractor facility.

VI. DELIVERY TERMS

Delivery shall be F.O.B Destination and shall occur in accordance with the delivery due dates provided in the above table.

FOB Destination means: The contractor shall pack and mark the shipment in conformance with carrier requirements, deliver the shipment in good order and condition to the point of delivery specified in the purchase order, be responsible for any loss of and/or damage to the goods occurring before receipt and acceptance of the shipment by the consignee at the delivery point specified in the purchase order; and pay all charges to the specified point of delivery. The contractor shall deliver all Line Items to:

DOC/NIST

Shipping & Receiving 325 Broadway ATTN: Ari Feldman Boulder, CO 80305

VII. INSPECTION & ACCEPTANCE

In addition to the inspection and acceptance terms articulated in 52.212-4, the Government reserves the right to perform such performance tests and evaluations as defined below to verify specified system performance. Such tests and evaluations, if performed, shall be conducted within the environment that the system is to be operated. The Contractor has the right to be present during the tests and evaluations, if performed, at the Contractor’s expense.

Performance Tests:

1. Optical inspection of circuits for obvious design flaws

2. DC Bias of circuits to test for nominal resistance, bias points

3. Small signal s-parameters of calibration kits

NIST may choose at its discretion to forego this part of acceptance testing.

A visual inspection of the equipment will be performed by the NIST COR to identify surface defects or any form of indication that any equipment was damaged during transport to NIST. The Government shall have sole discretion to require repair or replacement of damaged and/or nonconforming supplies at no cost to the Government. The Government at any time prior to acceptance shall reject the equipment due to defects and/or nonconformance. The vendor is responsible for latent defects discovered any time after final inspection. However, the extent of its liability shall be prorated over the useful life of the equipment.

Ownership of the equipment shall transfer to NIST upon acceptance by the Government.

The Government will test, inspect, and accept or reject the equipment within 10 working days of the receipt of the equipment unless otherwise indicated above. The Government reserves the right to conduct quality assurance testing to confirm that a given instrument(s) meets the manufacturer’s and/or the Government’s performance specifications. It is anticipated that the equipment will meet all manufacturer’s specifications and/or the Government’s performance specifications identified in the most recent operations and maintenance manual for each piece of equipment and/or in this document.

VIII. PAYMENT SCHEDULE

Advance payment is not authorized. The Contractor must invoice in arrears according to the payment schedule. The Contractor shall be paid, in accordance with Net 30-day payment terms, upon receipt and acceptance of a proper invoice, in accordance with the following schedule:

NOTE: Partial shipments and partial invoices will be accepted, unless otherwise requested and accepted by the Contracting Officer prior to award offer. Proposed payment schedules shall be submitted with vendor’s response to the RFQ for consideration.

IX. CONTRACTOR SUPPLIED MATERIALS

The contractor shall supply all parts, hardware, equipment, and labor required to perform the tasks listed.

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