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All Federal Grant Awards
Project Grant 1927546
Award Date
10/1/19
Completion Date
9/30/23
Dollars Obligated
$950K
Overview
Activity
5
Transactions
5
Subawards
Similar Awards
Federal Agency
National Science Foundation
Awardee
Astrileux Corp (PS3LNBG3PNV4)
Federal Grant Program
47.084
Assistance Type
Project Grant
Place of Performance
Berkeley, CA 94720, USA
Update #1
Update #2
SBIR PHASE II: NEXT GENERATION HIGH PERFORMANCE EUV PHOTOMASKS.
Posted 9/23/19
5
1
Mod #
Description
ReasonForModification
Federal Obligation
Date
Not listed
SBIR PHASE II: NEXT GENERATION HIGH PERFORMANCE EUV PHOTOMASKS. -THE BROADER IMPACT/COMMERCIAL POTENTIAL OF THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PHASE II PROJECT IS TO DRIVE THE NEXT GENERATION OF ADVANCED COMPUTING POWER AND PERFORMANCE BY MANUFACTURING INTEGRATED CIRCUITS (ICS) AT 7 NM AND SMALLER. TODAY'S CENTRAL PROCESSING UNITS (CPUS) CONTAIN 7.2 B CHIPS AND OVER 1.2 SEXTILLION CHIPS ARE MANUFACTURED PER YEAR. NEXT GENERATION TECHNOLOGY IS EXPECTED TO ENABLE ARTIFICIAL INTELLIGENCE AND MACHINE LEARNING THROUGH BOTH CONVENTIONAL COMPUTING AND POTENTIALLY NEW PARADIGMS FOR TRANSFORMATIVE APPLICATIONS SUCH AS SELF-DRIVING CARS AND SMART BUILDINGS, BUT NEW WAYS ARE NEEDED TO MAKE APPROPRIATE CHIPS. THE PROPOSED PROJECT WILL DEVELOP A TECHNOLOGY TO ADDRESS THIS NEED AS CHIPMAKERS MEET THEIR DESIRED GOALS. THE PROPOSED PROJECT ADDRESSES CHALLENGES RELATED TO HIGH VOLUME MANUFACTURING AT THE 7 NM NODE FOR LITHOGRAPHY TOOLS AND THEIR COMPONENTS. AN EUV PHOTOMASK, A HIGH COMMODITY COMPONENT, PATTERNS AND REPLICATES INTEGRATED CIRCUIT DESIGN INTO SILICON WAFERS. CURRENT EUV PHOTOMASKS HAVE A SUB-OPTIMAL MANUFACTURING YIELD OF ~65% AND SUFFER FROM DEFECTIVITY DURING FABRICATION OF ITS ARCHITECTURE. DURING OPERATIONAL USE THE PHOTOMASK SUSTAINS DAMAGE FROM THE DEBRIS GENERATED BY THE EUV PLASMA LIGHT SOURCE THAT IMPLANTS IN THE MASK AND INEVITABLY REPLICATES IN THE WAFER, DESTROYING THE INTEGRATED CHIP PATTERN. IN HIGH VOLUME MANUFACTURING, THESE ISSUES MANIFEST IN THE WAFER YIELD, THE REUSABILITY OF A MASK, AND DRIVE THE NEED FOR HIGH COST REAL-TIME INSPECTION AND METROLOGY. WE PROPOSE A NEW EUV PHOTOMASK WHICH PROMISES A HIGHER ROBUSTNESS TO DEFECTS, A HIGHER MANUFACTURING YIELD, BETTER UNIFORMITY AND MORE REUSABILITY OF MASKS IN OPERATIONS AND LONGER LIFETIME. THE GOALS OF THE PROJECT ARE TO EVALUATE NEW INTEGRATED ARCHITECTURE FOR THE EUV MASK DESIGN, DEVELOP A HIGHER YIELD FABRICATION PROCESS AND CHARACTERIZE THEIR EUV PERFORMANCE. MORE ROBUST ARCHITECTURES REDUCE CAPITAL OUTLAY REQUIREMENTS FOR IN-SITU METROLOGY AND INSPECTION AND ULTIMATELY BRING DOWN THE COST OF NEXT GENERATION ELECTRONICS. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.
$0
1/27/23
Not listed
SBIR PHASE II: NEXT GENERATION HIGH PERFORMANCE EUV PHOTOMASKS. -THE BROADER IMPACT/COMMERCIAL POTENTIAL OF THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PHASE II PROJECT IS TO DRIVE THE NEXT GENERATION OF ADVANCED COMPUTING POWER AND PERFORMANCE BY MANUFACTURING INTEGRATED CIRCUITS (ICS) AT 7 NM AND SMALLER. TODAY'S CENTRAL PROCESSING UNITS (CPUS) CONTAIN 7.2 B CHIPS AND OVER 1.2 SEXTILLION CHIPS ARE MANUFACTURED PER YEAR. NEXT GENERATION TECHNOLOGY IS EXPECTED TO ENABLE ARTIFICIAL INTELLIGENCE AND MACHINE LEARNING THROUGH BOTH CONVENTIONAL COMPUTING AND POTENTIALLY NEW PARADIGMS FOR TRANSFORMATIVE APPLICATIONS SUCH AS SELF-DRIVING CARS AND SMART BUILDINGS, BUT NEW WAYS ARE NEEDED TO MAKE APPROPRIATE CHIPS. THE PROPOSED PROJECT WILL DEVELOP A TECHNOLOGY TO ADDRESS THIS NEED AS CHIPMAKERS MEET THEIR DESIRED GOALS. THE PROPOSED PROJECT ADDRESSES CHALLENGES RELATED TO HIGH VOLUME MANUFACTURING AT THE 7 NM NODE FOR LITHOGRAPHY TOOLS AND THEIR COMPONENTS. AN EUV PHOTOMASK, A HIGH COMMODITY COMPONENT, PATTERNS AND REPLICATES INTEGRATED CIRCUIT DESIGN INTO SILICON WAFERS. CURRENT EUV PHOTOMASKS HAVE A SUB-OPTIMAL MANUFACTURING YIELD OF ~65% AND SUFFER FROM DEFECTIVITY DURING FABRICATION OF ITS ARCHITECTURE. DURING OPERATIONAL USE THE PHOTOMASK SUSTAINS DAMAGE FROM THE DEBRIS GENERATED BY THE EUV PLASMA LIGHT SOURCE THAT IMPLANTS IN THE MASK AND INEVITABLY REPLICATES IN THE WAFER, DESTROYING THE INTEGRATED CHIP PATTERN. IN HIGH VOLUME MANUFACTURING, THESE ISSUES MANIFEST IN THE WAFER YIELD, THE REUSABILITY OF A MASK, AND DRIVE THE NEED FOR HIGH COST REAL-TIME INSPECTION AND METROLOGY. WE PROPOSE A NEW EUV PHOTOMASK WHICH PROMISES A HIGHER ROBUSTNESS TO DEFECTS, A HIGHER MANUFACTURING YIELD, BETTER UNIFORMITY AND MORE REUSABILITY OF MASKS IN OPERATIONS AND LONGER LIFETIME. THE GOALS OF THE PROJECT ARE TO EVALUATE NEW INTEGRATED ARCHITECTURE FOR THE EUV MASK DESIGN, DEVELOP A HIGHER YIELD FABRICATION PROCESS AND CHARACTERIZE THEIR EUV PERFORMANCE. MORE ROBUST ARCHITECTURES REDUCE CAPITAL OUTLAY REQUIREMENTS FOR IN-SITU METROLOGY AND INSPECTION AND ULTIMATELY BRING DOWN THE COST OF NEXT GENERATION ELECTRONICS. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.
$50.0k
2/18/22
Not listed
SBIR PHASE II: NEXT GENERATION HIGH PERFORMANCE EUV PHOTOMASKS.
$0
10/6/21
Not listed
SBIR PHASE II: NEXT GENERATION HIGH PERFORMANCE EUV PHOTOMASKS.
$150.0k
3/25/20
Not listed
SBIR PHASE II: NEXT GENERATION HIGH PERFORMANCE EUV PHOTOMASKS.
$750.0k
9/23/19