Integrity and Reliability of Integrated CircuitS (IRIS), Phase III
Awarded Award Notice Posted
- Solicitation number
- DARPA-BAA-15-47
- Agency
- Defense Advanced Research Projects Agency Department of Defense
- Awarded
- Set-aside
- No set-aside
Opportunity facts
- NAICS code
- 541712 Research and Development in the Physical, Engineering, and Life Sciences (except Biotechnology)
- PSC
- Not on record
Notice details come from SAM.gov. Updated .
Notice text
Added: Jul 17, 2015 3:24 pm
DARPA is soliciting research proposals for a comprehensive exploration of the effects of extreme physical stresses on wear-out and aging mechanisms in CMOS FETs at 28nm and/or 14nm lithography node. The objective of the IRIS Program Phase III is to explore aging effects in both transistors and transistor interconnects to create predictive models and to test how precisely and rapidly specific wear-out mechanisms can be asserted, for the purposes of accelerating burn-in, aging, and wear-out.
See the full DARPA-BAA-15-47 document attached.
Attachments
| File | Type | Posted |
|---|---|---|
| DARPA-BAA-15-47_IRIS_PH3_Final_For_Posting_17July2015.pdf | ||
| DARPA-BAA-15-47_Attachment 1_Proposer Checklist.pdf |
Notice history
| Notice | Type | Posted |
|---|---|---|
| Integrity and Reliability of Integrate CircuitS (IRIS - Phase III) | Award Notice | |
| Integrity and Reliability of Integrate CircuitS (IRIS) - Phase III | Award Notice | |
| Integrity and Reliability of Integrate CircuitS (IRIS) - Phase III | Award Notice | |
| Integrity and Reliability of Integrated CircuitS (IRIS), Phase III | Award Notice |
On GovTribe
Work this opportunity on GovTribe
- Track it in your pipeline
- Find teaming partners
- Similar opportunities
- Ask GovTribe AI about this opportunity