Automatic Implementation of Secure Silicon (AISS)

The Defense Advanced Research Projects Agency seeks proposals to develop an automated design flow for integrated circuits that protects chips from security threats. The agency is soliciting research across two technical areas to streamline inclusion of scalable defenses into the design process and maximize exploration of security versus economic trade-offs while improving productivity. Proposals are due May 20, 2019 and the agency anticipates funding approximately $75 million over 48 months beginning in October 2019, divided into phases with demonstrations and reviews.

No set-aside designations apply. Research will involve developing modular and generated security engines and asset management infrastructure under NAICS code 541712 and PSC code R408, as well as demonstrating secure compute platforms through automated system synthesis and optimization for ARM and RISC-V architectures under NAICS code 541511 and PSC code D308. Multiple awards are expected across the two technical areas to incorporate defenses into the design flow for digital circuits and streamline security-related tradeoffs.