SATPC0033875 Tab 07 SOW.pdf

Title: Semiconductor Electrical Modeling for In-Space Memory Manufacturing

Duration: Jan 1, 2024 – Sep 30, 2024

Project Overview:

Semiconductor manufacturing is in a pressing need. With the increasing demand of semiconductor-based computing, memory chip enables the rapid prototyping and opens the era of new semiconductor chips performance boosting with highly efficient, low cost and high functionality of chips. Manufacturing the chips in the zero-G environment (i.e. “in-space manufacture”) through the inkjet printing process leads to the significant process complexity reduction attributed to the microgravity. Direct printing manufacturing is useful for fabricating the high-density memory as three-dimensional (3D) resistive random-access memory (RRAM) design with high process flexibility in a limited space supplement (e.g. all-in-one fabrication). These features are critical for NASA missions. Achieving the good performance, high memory window, good reliability, good accuracy, and good resolution on the memory devices are challenging in in-space manufacture. As emerging printing technology are being developed, physical models on semiconductor devices needs to be developed while through renovating the evaluation techniques towards the as-fabricated devices in order to maximize the in-space printable semiconductor technology.

he characterization techniques with high resolutions towards thin-film devices, and preventing the devices from permanent dielectric breakdown (i.e. compliance current limit setup).

The probe station (FormFactor) is with industrial standard semiconductor parameter analyzer (Keysight B1500 A), which has ultra-low leakage, ultra-low capacitance, and excellent chunk/ chamber shield bringing the high resolution (lowest current level detection ~pA). The set up also includes the pulse measurement on the 5 ns operation resolution which evaluate the memory as the computing primitives.

Our preliminary data has the current-voltage (I-V) characteristics, time-dependent speed evaluation (~ns), and numerical fitting for current transport mechanisms understanding. Chen have designed the microstructure of 3D trench with TEL, developed the process design kits specification and roadmap with Intel, and provided the testing structures for UW-Madison/ISU on the basis of device electrical characteristic prediction. In addition, the radiation effect on thin-film memory window and switching performance were investigated in our preliminary results (ISSRDC 2021, 2022, submitted to IEDM 2023).

The objective is to develop a passivation-removal function on current probe station as an end-point detection by mechanical etching. The goal is to enable future testing procedure on 3D structure trench for high density memory technology. To enable the memory integration, the oxide will be spin coated on the trench before the passivation removal process can be developed.

Silicon patterned trench will be tested for mechanical passivation removal capability.

will develop the required passivation-removal-probe feature before any memory on 3D structures can be measured.

est , evaluat , and validat the groundwork with thin film (e.g. ZnO) in vertical, crossbar and post-flight device characterization as the preliminary results for flight test scheduled in 202 and May 2024. haracterize the performance and reliability on printed memory by DC measurement after the test flights bringing the devices to the ground.

focus on semiconductor device properties of , especially the passivation remov capability, and thin film coated on the patterned wafer with sub-micron trenches, will be tailored as fundamentals of optimizing the memory structures, design, and further prototyping of in-memory computing. Based on benchmark of performance, current transport investigation, and defect detection in process, the deliverables can be advanced to the future oxide-based logic transistor-memory integration co-design for the NASA InSPA program.

Scope of work:

est the passivation removing probe set up on TEL trench wafer, metrology of the trench after mechanical removal of silicon. est the passivation removal probe station demonstration first-trial on TEL processed IMIMSi wafer (Figure 1). Removing the SiOx (100 nm) (I3) and expose TiN (M2) will be conducted. Conductivity with continuing testing I-V sweeps will be provided when M2 is successfully exposed. Memory reliability tests on both ground-developed and in-space manufactured devices as retention and endurance. The deliverables in the quarter include the IMIMSi trench structure electrical validation, data analysis on device performance, and experimental repeatability.

*Supportive Scope of work: functional DC I-V measurement will be conducted on memory device structures (e.g. crossbar, vertical, planar), if delivered any from ISU and UW-Madison.

Schedule

Timeline (Month)/deliverables

January February March April May June July August September

Phase 1 Kickoff meeting Spin-Coated Oxide Film Formation on Si Trench Report 1 Oxide Passivation Removal on Si Trench/Metrology Report 2 Pre- post- Expose Silicon Trench Report 3 Spin-coated Oxide Film Formation on IMIMSi Trench/Metrology Report 5 Apply Oxide Removal Test on IMIMISi trench Report 6 Soft breakdown e-test on M2/I2/M1 Final Report

Technical Milestones

ASU probe station is upgraded with reworking on positioners calibration for passivation-removal -probe module. To enable the memory integration, the oxide will be spin coated on the trench before the passivation removal process can be developed. Silicon patterned trench will be tested on the probe station for mechanical passivation removal capability. onduct the metrology analysis for removal capability. est the passivation-removal-probe set up on 1 μm- 1μm (pillar width-trench width) with spin coated oxide films for all the development.

Jan 2024-Feb 2024 - ASU probe rework and positioners calibration

- Recipe Development: Spin-coating oxide thin film on Si Trench

- Pre- and post-expose Silicon conductivity validation

Mar 2024-April 2024 - Passivation removal probe station on microstructures: testing on trench-patterned wafer

- Metrology analysis on oxide thin film spin-coated Si trench

April 2024- July 2024 - Passivation removal probe station demonstration first-trial on TEL processed IMIMSi wafer

-oxide thin film spin-coated IMIMSi trench

- Removing the SiOx (100 nm) (I3) and expose TiN (M2)

-Memory DC I-V tests on both ground-developed and in-space manufactured devices as retention and endurance

July 2024- September 2024 - Removing the SiOx (100 nm) (I3)/TiN (40 nm) (M2)/ SiOx (250 nm) (I2) and expose TiN (M1)

- Soft breakdown testing on M2/I2/M1

-Final Report

Budget Justification:

This funding is expected to be spent for the following session from Jan 15th , 2024 to September 30th, 2024.

1. Senior personnel support Summer salary is requested to support Principal Investigator for 0.3 summer month for the one-year project. be responsible for mentoring the graduate students for both doctorate and master students. In addition, will mentor the undergraduate researcher students in Semiconductor Device Research Laboratory.

Funds to support 1 PhD graduate research assistants (GRA) . The grad students will devote 100% level of effort for the academic year and 50% FTE during three-month summer for the one-year project. The grad students will be responsible for executing the research project on the topic of in-space manufactured semiconductors and device research (SEADS), deliver the results of the projects etc. Also, the graduate students will be responsible to train and mentor the undergraduate students for the fabrication process and characterizations.

Fringe benefits (Employee Related Expenses).

direct costs, estimates benefits as a standard percent of salary applied uniformly to all types of sponsored activities, and charges benefits to sponsors in accordance with the Federally-negotiated rates in effect at the time salaries are incurred.

An estimated cost escalation has been included in the out years. The rates used in the proposal budget are based on the current Federally-negotiated Rate Agreement plus annual escalation for out years. The estimated cost of ERE for the personnel effort allocated in this project, which is based upon the following rates for FY 2024. Note: PI salary requests are based on the individual current rate as stated in the University’s Human Capital Management system. full-time GRA effort 20 hours per week during the Academic Year and 40 hours per week during the summer.

2. Travel Support

Domestic travel costs cover expenses f conference meetings for presentations at yet-undetermined locations. IEEE IEDM, IEEE DRC, IEEE SISC, and ISSR&D are examples of possible conferences.

3. Facilities and Administrative costs.

Facilities & Administrative costs are using F&A rates approved by the Department of Health and Human Services.

4. Equipment The Keysight B1500A Semiconductor Parameter Analyzer will be .

5. Equipment or Facility Rentals/User Fees

The facility usage rate is . Total usage hurs are hours.

6. Tuition Remission Tuition for graduate students is included as a mandatory benefit for graduate students employed by the university and is charged to projects in proportion to the amount of the effort the graduate students will work on the project. Tuition charges are exempt from the Facilities and Administrative (F&A) costs. Below are the costs for one full student.

7. Other cost

The samples and devices will be shipped . FedEX, UPS, USPS or equivalent will be used for carrier, including the package and protection.