RFQ__NNG17619050Q_Q&A.pdf

RFQ# NNG17619050Q Q&A

1. Pinhole-Free SiO2 Deposition:

Would the deposition be done on a flat surface of a Si wafer, or on some structure? If latter, is conformal (step) coverage or gap fill required? What is the aspect ratio of the structure? What is the rough thickness for the SiO2 film(s)? Are they, for example, in the order of tens of microns or just a couple of angstroms?

a. The SiO2 deposition will be evaluated on flat silicon as well as a patterned niobium layer ~1500 A thick with near 90 degree sidewalls. A layer of ~3000 A SiO2 will be evaluated.

2. Substrate Size:

On page 1 and page 3, the SOW specified that the tool to be setup for 100mm wafers, with upgrade path to 6” and 8” wafers. Should Vendors include additional 6” and/or 8” clamping kits in the quotation body or should they be quoted as optional components?

a. Please quote the 6” and 8” clamps as optional components

3. Substrate Dimensions:

To achieve the specified 0.7 cm edge exclusion, please help provide the substrate fiducial details (e.g. thickness, major flat size, minor flat size, minor flat location, etc.) for the correct clamp kit design. Note that there are multiple SEMI standards for the same size of wafers.

a. For the 0.7 cm exclusion zone, it is fine to ignore the effect of the major and minor flats and just assume a circular exclusion zone. We typically use SEMI standard, n-type if the vendor would like to describe more specifics about the clamping mechanism and how it will achieve the spec.

4. Temperature Range: Please confirm if it is the 20-200C range.

On page 1 the document specified that the film will have to be under 140 C, so it makes sense where page 2 specified the temperature range being 20 C to 200C. However, page 6 also mentioned 20 to 400 C, which contradicted other specs in the SOW. We believe it should be 20 to 200C, and thus would like to confirm.

a. The 20-200 C range is correct and inconsistent verbiage can be disregarded. What was intended is an interest in a “low” temperature deposition below 140 C that achieves reasonable oxide performance and then allowing for up to 200 C deposition temperature for the best quality oxide.

5. Temperature Measurement:

Typically Vendors have limited way to measure actual temperature on the substrate, in real time, with tight +/- 2C control. We could, however, measure the temperature on the lower electrode, where substrate sits. Would this approach be acceptable for NASA?

a. The temperature measurement method is acceptable. NASA plans to evaluate wafer temperature during oxide growth recipes using wax temperature “dots”. Having such measurements correlated with a thermometer readout is acceptable.

6. Chamber Pressure:

Is it possible to somewhat relax the 1e-7 Torr base pressure requirement to, for example, 5x10-6 Torr? Typical ICPCVD process regime would be in the order 1-10 mTorr. Also is it OK to use o-rings and VCRs on some of the ports on the process chamber?

a. To ensure there is not a water or air leak into the chamber, we require the ability to pump below 2e-6. We chose 1e-7 – which is over an order of magnitude below the

RFQ# NNG17619050Q Q&A

water peak. So this requirement can be relaxed – but must still be in the 10-7 range to ensure that we have leak tight vacuum during the film growth.

7. Loadlock Motion Arm: Is it acceptable that our design wouldn’t require a motion arm with lift mechanism for load/unload wafers? Our approach is to keep the wafer and the chamber clamping mechanism in the same plane.

a. The substitute mechanism for wafer load/unload should be described in detail. But the vendor plan sounds acceptable.

8. 3kW ICP Power: Is a 2 kW, 2 MHz ICP power acceptable? Our standard design incorporates 2 kW power and has proven very reliable for low temperature ICPCVD films.

a. The smaller size of power supply should be acceptable. The immediate need is high quality SiO2 films on 4” wafers. So sufficient information that this can be achieved with the provided power supplies should be supplied.

9. The specifications mention that load lock needs to be designed for 4" and 6" wafers but suitable for 8” wafer too. Please clarify whether the system has to compatible for 4” and 6” wafers or for up to 8” wafers.

a. We require compatibility with 8” wafers for chamber size and passthrough gate valve from the loadlock.