DARPA-BAA-14-16_Amendment_1__final_for_posting_26Mar2014_.pdf

Broad Agency Announcement Supply Chain Hardware Integrity for Electronics

Defense (SHIELD) Microsystems Technology Office

DARPA-BAA-14-16

March 3, 2014

(Amendment No. 01: As amended through 26 March 2014)

Table of Contents

Part I: Overview Information Part II: Full Text of Announcement

Sec. I: FUNDING OPPORTUNITY DESCRIPTION A. Program Objectives B. Program Structure C. Technical Areas

Sec II. AWARD INFORMATION A. Fundamental Research

Sec. III: ELIGIBILITY INFORMATION A. Eligible Applicants B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and Organizational Conflicts of Interest C. Cost Sharing/Matching

Sec. IV: APPLICATION AND SUBMISSION INFORMATION A. Address to Request Application Package B. Content and Form of Application Submission

Sec. V: APPLICATION REVIEW INFORMATION A. Evaluation Criteria B. Review and Selection Process

Sec. VI: AWARD ADMINISTRATION INFORMATION A. Selection Notices B. Administrative and National Policy Requirements

Sec. VII: AGENCY CONTACTS Sec. VIII. OTHER INFORMATION

A. Intellectual Property Procurement Contract Proposers B. Non-Procurement Contract Proposers – Noncommercial and Commercial Items (Technical Data and Computer Software) C. All Proposers – Patents D. All Proposers – Intellectual Property Representations E. Other Transactions (OTs):

Part I: Overview Information

• Federal Agency Name – Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office/MTO

• Funding Opportunity Title – Supply Chain Hardware Integrity for Electronics Defense

(SHIELD)

• Announcement Type – Initial Announcement

• Funding Opportunity Number – DARPA-BAA-14-16

• Catalog of Federal Domestic Assistance Numbers (CFDA) – 12.910 Research and

Technology Development

• Dates o Posting Date: March 3, 2014 o Abstract Due Date: April 1, 2014 (4pm Eastern) o Proposal Due Date: May 30, 2014 (4pm Eastern) o Proposer’s Day: March 14, 2014 (See DARPA-SN-14-22)

• Anticipated individual awards – Multiple awards are anticipated.

• Types of instruments that may be awarded -- Procurement contract, grant, cooperative agreement or other transaction.

• Any cost sharing requirements - None

• Agency contact o Mr. Kerry Bernstein The BAA Coordinator for this effort can be reached at

DARPA/MTO

ATTN: DARPA-BAA-14-16

675 North Randolph Street Arlington, VA 22203-2114 DARPA-BAA-14-16@darpa.mil mailto:DARPA-BAA-14-16@darpa.mil

Part II: Full Text of Announcement

Sec. I: FUNDING OPPORTUNITY DESCRIPTION

The Defense Advanced Research Projects Agency often selects its research efforts through the Broad Agency Announcement (BAA) process. This BAA is being issued, and any resultant selection will be made, using procedures under Federal Acquisition Regulation (FAR) 35.016 and the Department of Defense Grant and Agreement Regulatory System (DoDGARS) Part 22 for Grants and Cooperative Agreements. Any negotiations and/or awards will use procedures under FAR 15.4, Contract Pricing, as specified in the BAA (including DoDGARS Part 22 for Grants and Cooperative Agreements). Proposals received as a result of this BAA shall be evaluated in accordance with evaluation criteria specified herein through a scientific review process.

DARPA BAAs are posted on the Federal Business Opportunities (FedBizOpps) website, http://www.fbo.gov/, and, as applicable, the Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA.

DARPA is soliciting innovative research proposals in the area of supply chain protection of electronic components. Proposed research should investigate innovative approaches that enable revolutionary advances in science, devices, or systems. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice.

By nature of the application, the systems which the United States depends upon for national security places severe demands on the electronic components comprising them; a failure in any one of these components can put warfighter lives as well as missions at risk. It is critical, then, that these components perform as expected and for their full specified lifetime. The erosion in the securing and the control of industry as well as government electronic component supply chains, however, presents a growing threat to national security. Recycled, rejected, or remarked authentic parts and non-authentic counterfeit electronic components are increasingly widespread throughout the defense supply chain; over the past two years alone, more than one million suspect parts have been associated with known supply chain compromises1. Independent distributors have indicated that anywhere from 0.5% to 35% of their incoming products for some part categories are suspected counterfeit2. Threats from counterfeit parts of unknown provenance may be associated with: their questionable quality control, unknown age/wear-out; uncertain version vintage; and/or uncertainty about whether the parts meet specifications and are free from adulteration.

1 “Inquiry into Counterfeit Electronic Parts in the Department of Defense Supply Chain”, Report of the Committee on Armed Services, United States Senate, May 21, 2012, pp i-ii 2 “Can EDA Combat the Rise of Electronic Counterfeiting?”, Matthew Sale (USNSWC, Crane, IN, US), Design Automation Conference (DAC) 2012, Session 8.1, 5 June, 2012 http://www.fbo.gov/ http://www.grants.gov/

Many counterfeit parts sold to contractors come from legitimate independent distributors; with the best of intentions, but lacking effective screening techniques3, these distributors may be at risk for passing along bogus components. Because of this, a policy of excluding distributors who have sold counterfeits from future government sales provides some improvement in security, but it does not adequately address the problem. The globalization of semiconductor production, packaging, and electronic module assembly, the low cost of entry and the technical sophistication required to produce counterfeit parts are factors that will allow counterfeiting to continue to grow. Extended DoD design and acquisition cycles of 10 years or more, and product service lifetimes of perhaps 30 years causes components to become obsolete before a DoD system is retired. Parts that formerly cost $10 each can become worth thousands of dollars more once they become obsolete, thus incentivizing further counterfeiting.

Chain of custody, once an effective means of safeguarding component provenance, is no longer able to effectively counter the infusion of counterfeit parts due to the global nature of today’s extensive international supply chain. For larger systems, integrated circuits and subassemblies may pass through many hands on multiple continents before they are ultimately installed in their final application; each stop along the way exposes the assembly to additional potential compromise. Non-destructive, high-volume detection of counterfeit electronics, where it even exists, can be expensive and time-consuming, due in part to the growing size and complexity of integrated circuits, and the need for comprehensive analysis of large quantities of parts. Current methods of detection involve a variety of techniques ranging from functional testing to physical inspections. In general, these methods are not fully effective, as well as too expensive, too slow, and too easily circumvented. Because of the lack of an effective deterrence, counterfeiters create and distribute illicit parts with impunity at minimal cost, reaping millions of dollars in revenue lost to the IP owner and the OEM. In addition to the risk, replacing these counterfeit components once they are discovered costs the Government millions of more dollars.

The threat space associated with the infiltration of counterfeit electronic components in the supply chain is extensive, and includes:

- Recycled components removed from used printed circuit boards and sold as new;

- Unlicensed overproduction of authorized components built by a foundry;

- Test rejects and sub-standard component yield fallout sold as new, high quality parts;

- Parts remarked with falsely elevated reliability grade or newer date of manufacture;

- Clones and copies of original components, which may be of extremely low quality, or which may include altered or hidden additional functionality; and

- OEM components that are covertly repackaged into new product form-factors and then used in unauthorized applications.

A widely-adopted supply chain security assurance capability is urgently needed. Such a solution must exhibit a few key characteristics. Supply chain authentication must be:

- Extremely low cost, with minimal impact to the component manufacturer, distributor, or end-user, as well as to the host component itself;

- Effective at mitigating most supply chain security threats;

- Be simple, very fast, and executable by untrained operators;

3 “Can EDA Combat the Rise of Electronic Counterfeiting?”, Matthew Sale (USNSWC, Crane, IN, US), Design Automation Conference (DAC) 2012, Session 8.1, 5 June, 2012

- Trustworthy, reliable, and prohibitively difficult to spoof;

- Executable at any place and at any time along the supply chain, providing instant results on-site;

- Performed using a minimum of specialized, inexpensive interrogation equipment;

- Standardized and widely adopted by government and industry;

- Manufacturable in high volume using standard foundry processes; and

- A value-add to the end-product, recognized and requested by the component consumer.

The DARPA SHIELD Program intends to develop an advanced supply chain hardware authentication technology capability. Specifically, DARPA is soliciting innovative research and development proposals to create extremely small electronic chips hosting specific advanced capabilities described below, for use in the authentication of the host electronic components to which they are physically attached.

Table 1 Glossary

Dielet Extremely small computer chip developed during SHIELD Hardware Root-of- Trust An incorruptible, immutable hardware identity reference

Key A 256-bit cipher code, stored on dielet and on a secure server, used to secure the dielet authentication operation

Test Site Limited hardware proof of concept chip without full product functionality

Sensor Physical hardware structure on SHIELD dielet that passively detects intrusions compromising security

Probe A device attached to a communication appliance that powers the SHIELD dielet

IP Intellectual Property CONOP Concept of Operations DFM/DFY Design for Manufacturability/ Design for Yield PFA Probability of False Alarm PD Probability of Detection OEM Original Equipment Manufacturer GFE Government-Furnished Equipment IC Integrated Circuit CDR Critical Design Review DSS Digital Signature Standard CMVP Cryptographic Module Verification Program

FITS Failure rate of a component, measured in Failures-in-Time over the program

KPOH Lifetime of a component, measured in thousands of power-on-hours

BOM Bill of Material, a list of components comprising a given assembly

A. Program Objectives

The SHIELD Program will provide a secure hardware root-of-trust which, when co-packaged with an electronic component, will provide it with a unique, permanent identification that is nearly impossible to copy or alter. This root-of-trust will be used to authenticate the provenance of electronic components in an assembly as they travel through the supply chain, as well as by the final consumer of the assembly to occasionally re-authenticate the composition of its final installation throughout its lifetime. Superior dielet designs will contain six critical hardware assurance features:

1. A hardware root-of-trust cryptographic key storage which is prohibitively expensive and time-consuming to reverse-engineer;

2. A complete, compact, on-board key encryption engine, capable of encrypting an external challenge using its on-board cryptographic key; the cryptographic key never leaves the SHIELD dielet. The message will be decrypted using the cryptographic key stored in a secure server database;

3. A physically-fragile but electrically-robust dielet which can be embedded in the host component's electronic packaging. The dielet self-destructs upon any attempts to physically open, remove, or transfer it from its host component using standard reverse-engineering de-processing techniques;

4. Unpowered, passive sensors that record attempted compromises to the authenticator dielet and potentially other operations on the overall packaged assembly such as soldering or de-soldering;

5. Inductive or RF communication and powering to allow contactless operation; and

6. Built-in dielet resiliency against power-based component exploits or attacks.

The threat space associated with hardware attacks is substantial, and spans the entire design process, fabrication, and distribution of a component. While no single supply chain solution can protect the entire range of vulnerabilities, SHIELD will provide near-100% security assurance against the six most common counterfeit modes currently being seen in the industry, listed on page five.

To assure that such a device can fulfill the above objectives, additional design properties should be considered in superior design proposals.

7. Hardware attacks often leverage the alteration of various re-writable data storage structures, to reconfigure the given device into an alternative, unexpected machine state4.

Any rewritable storage included in designs must be carefully assessed for its security.

8. Components used in sensitive assemblies often have very specific, critical reliability targets. To not interfere with the reliability of the host component in any way, the offered SHIELD dielet proposal must be completely stand-alone, and should not touch or interact with the host chip in any way. Isolation from the SHIELD dielet allows the host to retain its original reliability. Potential reliability impacts include the package alterations needed to carry the dielet, and unintended inductive or RF coupling impacts on the host device during dielet activation. Both are studied in this program, and are described below.

4 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.prd29-genc-009492c/ch01s03s03.html

9. To maintain operational security, the inductive or RF probe and dielet must be in the immediate vicinity of each other to be able to communicate. The personalized cryptographic key information on the dielet must never be communicated off of the dielet, similarly, the key information on the server should never be released.

10. To be used ubiquitously and adopted by industry as well as government, the entire proposed CONOP, including the SHIELD dielet, needs to be extremely inexpensive to acquire, implement, and execute.

11. Finally, to minimize the physical size, power consumption, and cost of the SHIELD dielet, CONOP complexity should be pushed up to the secure server wherever possible, while still fulfilling the goals of the program.

The example CONOP, which will be realized during this program, demonstrates how SHIELD authenticates a given component. The tester uses an inexpensive appliance, perhaps a repurposed smartphone, which has an inductive or RF probe plugged into it. The component to be tested is probed with this inductive/RF probe immediately above where the SHIELD dielet is embedded.

Besides RF or inductive powering of the dielet, the appliance communicates via RF or induction with the dielet, uploading an unencrypted dielet serial ID which is associated with that host component. The OEM’s secure server then responds by issuing a random challenge “question” which is downloaded through the inductive/RF probe to the SHIELD dielet. The on-board encryption engine encrypts the challenge using its on-board, securely-stored cryptographic key and sends the encrypted “answer” back up to the secure server. The server unencrypts the answer using its cryptographic key, and compares it to the original challenge for authentication. As part of the encrypted reply, the server also receives the status of the passive sensors to verify the integrity of the SHIELD die itself, and then increments a counter tracking the number of times that dielet has been interrogated. A flow diagram of the example CONOP is shown in Figure 1 below.

Figure 1 SHIELD Concept of Operations. Black is unencrypted Query/Response, Red is the Cryptographic authentication, Blue is the sensors and appliance data transfer.

In volume production, it is anticipated that in lieu of a hand-held inductive/RF probe, automated scanners installed on robotic assemblies similar to current automated component installation tools will be used to improve thru-put and accuracy. The handheld probe however will be retained for use by the end-consumer to randomly revalidate the integrity of the installed system as desired, after delivery. The SHIELD demonstration in Phase 3 will use only handheld probes for demonstrating proof-of-concept.

It is likely that new industry hardware security standards will emerge as a result of the solutions developed by SHIELD performers. DARPA expects to engage with transition partners picking up SHIELD solutions who will pursue establishing related standards for hardware assurance.

B. Program Structure

The DARPA SHIELD program will be structured to achieve:

1. The development of fundamental, on-dielet hardware technologies needed;

2. The design and technology integration of the host dielet; and

3. The deployment and exercising of an exemplary supply chain authentication scheme, including inductive/RF probes, networks, servers, and appliances.

Work is organized into three separate technical areas, and execution of the project will span up to three distinct phases.

The DARPA SHIELD program structure is described below and shown graphically in Figure 2.

The program is organized in a manner that encourages performer teaming. Consistent with Section V, preference will be given to proposals that offer collaborative, complete solutions which address all three of the main technical areas. DARPA SHIELD will, however, consider stand-alone proposals for developing concepts in Technical Area 1 and Technical Area 3.

Further, DARPA will also consider stand-alone Technical Area 3 proposals which on its own is comprised of multiple collaborative performers rather than a single performer.

Figure 2 DARPA SHIELD Program structure

DARPA wishes to leverage the inputs of smaller institutions which may not be resourced to participate in full solutions, but which have compelling ideas for particular technologies identified below. In support of smaller potential contributors, a proposer offering work in multiple phases may be required to integrate the output of other prior-phase performers into their deliverable. All proposal descriptions should clearly define and separate the work offered for each of the Technical Areas. Work offered should be identified by Technical Area, so that portions of proposals may possibly be treated as “stand-alone” and selected independently for funding, if needed.

Groups that are interested in composing a comprehensive teaming proposal may access the DARPA SHIELD Teaming website bulletin board at https://sharepoint.extranet.darpa.mil/sites/mto/SHIELD/SitePages/Home.aspx to explore collaborations with other possible proposing groups. To request an account, please email the request to the BAA-14-16 mailbox at DARPA-BAA-14-16@darpa.mil

C. Technical Areas

Development of the SHIELD concept will be executed in three distinct technical areas, and completed in up to three phases, each with their own tasks, deliverables and deadlines. The period of performance for each of the technical areas is shown in Figure 2. The technical areas and their tasks and deliverables by phase are described below.

I. Technical Area 1: SHIELD On-Board Technology Phase 1 Only The desired level of supply chain hardware assurance to be provided by DARPA SHIELD requires novel, chip-borne technology components, which will need to be integrated into the existing design platform. Those technology elements and their desired characteristics include:

A. Secure Cryptographic Key Storage Technology.

Secure cryptographic key storage of up to 256 bits in length is required on the dielet to sustain cryptographic-level authentication of the product. A successful key storage technology is:

i. Exceedingly difficult to reverse-engineer;

ii. Effectively incorruptible;

iii. Self-destructive upon reverse-engineering or tamper attempts - exquisitely fragile, while still extremely reliable under normal use conditions;

iv. Economically personalized with unique serial ID and cryptographic key information in volume production.

v. Compatible with, and ideally available in, the chip process technology selected by performers for the dielet’s fabrication.

vi. Capable of storing keys that are compliant with Suite B cryptographic algorithms.

B. Passive Sensors Sensors are central to a robust SHIELD solution, to monitor the integrity of the authentication dielet itself, and to alert the auditor if a given host component has been compromised. Onboard sensors must:

https://sharepoint.extranet.darpa.mil/sites/mto/SHIELD/SitePages/Home.aspx mailto:DARPA-BAA-14-16@darpa.mil

i. Passively sense while being unpowered, and be read only when being powered;

ii. Be readable only, be permanently altered by the exposure, and be non-resettable in any way;

iii. Be inexpensively integrated into a conventional CMOS process without impacting the host process adversely;

iv. Be small enough to fit in the SHIELD dielet form-factor and specification;

v. Have an appropriately-tuned sensing threshold value, in order to prevent false positives caused by safe, existing exposures encountered throughout the current supply chain.

Multiple potential sensing modalities and technologies are of interest. Proposers are encouraged to suggest specific innovative sensing modes that will ensure the component’s security, or may provide sensors that passively sample for conventional, known threat modes. Examples include:

1. X-Ray: to make sure the dielet or the host part has not been reverse-engineered;

2. Light: to verify the part has not been opened or removed from its original host, sensitive to various wavelengths;

3. Temperature: to determine if the component has been recycled from an existing circuit board by melting the solder mounting it to its current printed circuit board.

4. Multiple interrogations: to counter dielet reverse-engineering by inserting delays of 1 second or more between concurrent interrogations.

Proposers are free to submit sensing technology development proposals which sense only a single threat mode, a subset of all the possible threat modes, or a comprehensive sensor that responds to all known potential threats.

C. Communication/Power Transmission Technology

Technology improvements will be needed to improve inductive/RF coupling efficiency so that very small form-factor devices can be used to power the dielet and to communicate with it. It is desirable to be able to power a dielet, pass a challenge message to it, and receive the encrypted reply in 2 seconds or less. Performers will determine the appropriate communication bandwidth necessary to support this latency while passing 256 bit key words, a 64 bit serial ID, random encryption challenges, and much shorter sensor output words. Proposers are invited to suggest technologies which provide ultra-high efficiency coupling between the on-dielet inductive coil or RF antenna, and the interrogating appliance. Solutions offered must couple the dielet to the appliance only when the appliance’s probe is in its immediate vicinity. The probe otherwise should not emanate significantly beyond the dielet, nor be able to link to other external devices.

Please note that communication to the SHIELD dielet should not be via conventional RFID technology; but rather only by inductive or RF coupling to another device within a few millimeters of the host component’s package.

D. Manufacturing/Process Technology Multiple adjunct process and manufacturing alterations to conventional CMOS fabrication technology may be required to produce SHIELD dielets in volume, with the desired new capabilities, and at the target of less than a penny per dielet. Technical Area 1 manufacturing / process challenges which require performer attention include:

1. Wafer thinning technologies necessary to produce and support SHIELD wafers that are potentially 10µm or less in thickness, as may be needed to build dielets that are 100µm x 100µm in size;

2. Integrating disparate sensor and key storage technologies into a common process;

3. High volume, precision personalization of each dielet with a unique serial ID and cryptographic key;

4. New test technologies needed to check the tiny dielets, i.e. contactless testing, test coverage protocol, application-specific test patterns;

5. An economic production solution for dicing, picking, and handling microscopic dielets that are approximately100μm x 100μm in size;

6. The means of assuring that reliability and lifetime of the SHIELD dielet matches that of the host component. Performers should assume host components which support 100 KPOH lifetimes, at no more than 3 FITs, and that SHIELD will be used for under 1 power-on-hour over its entire life.

Acceptable solutions may include 3D integration technology, if it can be shown that the resulting device assembly achieves the identified program goals, including cost.

Technical Area 1 is developed in the following program structure.

E. Technical Area 1/Phase 1: Technology Development Months 1-18

Phase 1 for the Technical Area 1 will be devoted to the development of the underlying fundamental devices, materials, and/or structures which realize the specific on-board capabilities defining SHIELD. During the execution of Phase 1, chip test sites prototyping the intended embodiment of these devices, materials, or structures must be designed, fabricated, and characterized, demonstrating specific desired capabilities.

Prospective solutions will be expected to accommodate and support the SHIELD target specifications shown in the Program Objectives section (Section A, Page 9). This demonstration will serve as a prototype for the specific solution to be used in the SHIELD Phase 2 vehicle.

Phase 1 tasks include:

1. Delivery of a fully-described hardware-based solution for required technical capability, including computer models of behavior rooted in hardware (i.e.

COMSOL, SPICE, finite element electromagnetic modeling, etc.). These models will be made available to the Technical Area 2/Phase 2 SHIELD chip integrator in a format that allows the integrator to generate a behavioral of the larger, assembled dielet.

2. The design and build of a hardware proof-of-concept test site for the intended realization of the proposed technology. Performers must sufficiently:

a. Exercise a specific realization of their proposed technology in an exemplary hardware application setting. The setting of the demonstration in the hardware test site should emulate conditions expected in actual placement in a host package.

b. Characterize performance, reliability and quality of the test site, for its response and sensitivity to temperature, voltage, process tolerance, defect modes, light intensity, altitude, x-rays, etc. The performers must establish the suitability of their technology when placed in a host component to be protected.

3. Verification of technology compatibility to conventional IC manufacturing process. Performers will establish manufacturing requirements for their technology, and verify that it can inexpensively and reliably be retrofitted to an existing process without compromise to the base process. If any modifications to existing conventional IC processing will be required, detailed descriptions of such modifications must be included. Examples include:

a. An impact statement, describing the anticipated response of base technology to the performer technology’s insertion;

b. The specific insertion point in the existing process;

c. New required materials or films to be introduced into the manufacturing process;

d. New tooling required to accommodate SHIELD features;

e. New processes associated with the technology assertion; recipes, depositions; techniques, implant doses and energies, temperatures, pressures, times, process endpoint detection;

f. Required line metrology additions to assure adequate yield and quality monitoring;

g. The re-entry point of SHIELD dielet hardware back into conventional processing.

h. Novel SHIELD dielet passivation, for protection/isolation in packaging, and technology compatibility to the passivation.

4. Layouts of specific technology reductions-to-practice, to be provided to the Phase 2 chip design integrator. The performer will identify layer names and compositions, alignment markings, signal references, etc. for integration into the design automation environment chosen by the Technical Area 2/Phase 2 designer.

5. Description of specific test conditions and a test pattern file, in an integrator-specified format. This is needed to check the specific technology reduction at dielet’s final test.

6. Development of a fully defined interface specification for the technology. A defined interface will facilitate its integration and use in SHIELD Phase 2 tasks.

F. Technical Area 1/Phase 1 Responsibilities

Technical options and responsibilities in Technical Area 1 will reside entirely with the performer and should be addressed in the offered proposal. Responsibilities to be handled by the performer include test site design, fabrication, and characterization, as well as operational physics, materials and structural choices.

II. Technical Area 2: SHIELD Dielet Design & Integration Phase 1 and 2 Only

SHIELD Technical Area 2 will integrate technologies developed in Phase 1 of the program onto a microscopic dielet carrying the necessary logic, to achieve a completely autonomous supply chain authentication prototype device. The extremely small chip will contain a full 256 bit encryption engine, secure and personalized encryption key storage, sensors that detect component compromise, inductive/RF communication and power, and the logic necessary to realize the interface to the secure server. SHIELD authentication dielets will be fabricated, tested, and characterized during Phase 2.

A. Technical Area 2/Phase 1: Design Months 1-18 In Technical Area 2/Phase 1, performers will design the logic realizing the onboard encryption engine, and the interface logic necessary to successfully communicate with the inductive/RF appliance. Proposals for Technical Area 2 must introduce innovative means of achieving required function economically in both device count and power, in order to meet the specifications of the program. The performer must provide block diagrams, state machine diagrams, timing diagrams, simulation outputs, flowcharts and other figures to illustrate the dielet architecture. These figures should guide the high-level design representation, and will be used in design reviews.

B. Technical Area 2/Phase 1 Tasks:

1. Define a SHIELD Design Environment: Performers will configure an engineering design automation environment that will support the development of the SHIELD dielet and the incorporation of its protection technologies. This design methodology must use conventional industry design descriptors and be capable of carrying the SHIELD program from initial design through design checking, simulation, power estimation, hardware build, test pattern generation, and electromagnetic interference checking, Performers will provide the adopted conventions to other SHIELD performers providing design inputs, in order to define input data syntax and data formats.

2. Develop a SHIELD logic design description, expressed in an appropriate high-level design language: The validated, verified logic design will comprise: a complete standard 256 bit encryption engine which responds to random challenges; the evaluation of onboard sensors; and the porting of network communication to the dielet’s logic. The performance of the design should be sufficient to be able to retire complete authentication transactions in approximately 2 seconds, which includes:

a. Powering the dielet;

b. Uploading the serial ID to a secure server, and downloading an unencrypted random challenge back down to the dielet; and

c. Encrypting the challenge and reading the onboard integrity sensors on board the dielet, then uploading both back up to the host server for decryption and comparison.

3. Provide Encryption: Potential SHIELD performers should propose a security scheme that provides at minimum the equivalent level of security as 256-bit AES, and which can be accommodated by the SHIELD dielet’s form factor, area, and available power.

Only open standard industry encryption designs will be used, but are the proposer’s choice. DARPA SHIELD is concerned with the development of hardware technology for supply chain authentication; consequently, the development of new encryption algorithms and standards are not part of the program and should not be offered by proposers. Only CMVP-verified encryption content may be used in the design.

Performers are encouraged to use 3rd party certified IP when available. Although discouraged from doing so, performers may elect to validate their own alternative implementation of industry standard encryption algorithms via CMVP, if the SHIELD schedule allows. Proposed designs must prevent the attacker from compromising the cryptographic key, and also must be built so that alternative encryption algorithms may later replace the performer’s implemented encryption, if desired by subsequent industry users. The design should also prevent frequent repeated interrogation of the chip that might be used by an attacker to attempt to divine the cryptographic key. No network security certificates of any kind should be stored on the SHIELD dielet.

4. Design in Needed Performance: If the proposed design is a synchronous clocked machine, then the performer is free to choose the onboard minimum or maximum clock rates needed to support on-dielet transaction retirement rates of 1 second on chip, within the available power envelope on chip (see next paragraph). Including high performance network latencies, total transactions should be completed in less than approximately 2 seconds.

5. Estimate power for the onboard logic and sensors: Power estimation must be performed, and the total power needed for the proposed dielet assembly must be accommodated by the available power. Dielet power can be sourced by the inductive or RF power design, at the prerogative of the proposer. It is anticipated that SHIELD dielet designs will be limited to approximately 50µW, order-of-magnitude. The design of the inductive or RF powering and communication circuitry including scheme dependent power conditioning must be supported by rigorous simulations and/or experimental demonstrations, as appropriate. Supply voltage is to be determined by the proposer, and default supply voltage tolerances will be +/- 10% unless proposers justify alternative tolerances. Power supply conditioning should be included in design if needed.

6. Integrate Technology: Technical Area 2 performers should closely coordinate with relevant Technical Area 1 performers to insure that:

a. The Technical Area 2 performer has a clear path for implementing Technical Area 1 technologies; and

b. The Technical Area 2 performer has a design and fabrication plan in Technical Area 2/Phase 2 showing how the integrated design, comprising logic and powering/communications circuitry, will be completed successfully in Phase 2.

c. Storage technology for the cryptographic key should be identified by the end of Technical Area 2/Phase 1; its implementation should be consistent with the Technical Area 1/Phase 1 key storage technology developed.

7. Create and Model SHIELD physical design: SHIELD circuit design modeling will verify that the physical implementation of SHIELD is robust across process, voltage, and temperature. SHIELD dielets should be functional across a +/- 3σ composite process distribution window, and at temperatures from 0-35deg C. The dielet should survive temperature exposures of -55deg C -125deg C. SHIELD dielets should also be functional across the +/- 3σ voltage window determined from the design of the power conditioning scheme selected. If performer design solutions are synchronous, then early mode/late mode timing models using best case/worst case models will be developed to ensure functionality and reliability of the embedded SHIELD dielet.

8. Fabrication implementation plan: the process technologies to be used in Phase 2 should be clearly defined, along with the intended candidate fab(s) or vendor(s) that will build the proposed design, the schedule checkpoints when submissions will be made, and how the new adjunct technologies required onboard the dielet will be accommodated by the fabrication facility selected.

9. Interface to Phase 1 Technologies: Suitable design interfaces and standards will be established and planned to facilitate the integration of Phase 1 technology components into the SHIELD dielet design. Phase 1 technologies will be added as IP blocks on the SHIELD dielet, including voltage level shifting, timing changes, and signal buffering as needed to effectively couple the IP to the chip.

10. Layout dielet design in industry standard format: Completed designs will conform to industry standard layout formats to facilitate entry into conventional fabrication submission systems. Successful proposers will apply insight and experience to optimize DFM and DFY, proposing solutions which insure high yielding SHIELD devices that are defect-resilient and process-tolerant.

11. Develop a test pattern generation and testing methodology: Successful proposers will develop the test pattern generation and testing strategy, and automated verification capabilities needed to thoroughly test (a) the SHIELD die, its new on-board technologies, and its sensors; and (b) the packaged host component. Testing must assure full SHIELD and host component functionality, economically and with as few patterns as possible. The SHIELD program depends on the yield, quality, and reliability of the new assembly to not compromise those of the original host component without SHIELD.

12. Support a Critical Design Review: Before proceeding with Phase 2, DARPA will review the performer's detailed plans for subsequent phases, and will assess whether the proposed approach is likely to result in a satisfactory SHIELD dielet solution before proceeding to Technical Area 2/Phase 2. To support that decision, the performer will support a Critical Design Review. The items listed above will be major inputs into the CDR. The performer will need to prepare analyses and reports, and provide inputs including experimental results where appropriate to substantiate feasibility of their SHIELD dielet design, and that it is ready to proceed to implementation. Significant remaining risks and associated mitigation plans should be identified.

C. Technical Area 2/Phase 2: Integration and Fabrication Months 19-36

In Phase 2 of Technical Area 2, design performers will incorporate Technical Area 1’s specific instantiations of Phase 1 performer technology solutions into their Phase 1 dielet chip design, for inclusion in the demonstration vehicle. After both final design checks and process audits, designs will be fabricated in anticipation of Phase 3 demonstrations.

D. Technical Area 2/Phase 2 Tasks:

1. Design full SHIELD dielet, ready for fabrication, with all required functionality including inductive or RF powering and communications; self-protection features;

core digital engine: In Phase 2, dielet physical designers will incorporate the technologies from Technical Area 1/Phase 1; and the base logic design created in Technical Area 2/Phase 1. The performer will complete final checking of the resulting assembly. During wafer manufacturing, performers will generate test patterns, and prepare for hardware evaluation.

2. Fabricate SHIELD dielet: Performers will release the design to manufacturing, and monitor SHIELD dielet wafers as they progress through manufacturing; they will intercept the hardware at critical process line insertion entries and exits for any new technology introductions. Performers will track process metrology and in-line monitors for SHIELD parts to assure dielet functionality for Phase 3 technology reduction. For the SHIELD program, dielet fabrication may be accomplished at US or foreign fabrication facilities, although post-program transition partners may later impose restrictions. Intended fab sites should be specified in the proposal.

3. Test, characterize, and assess reliability of SHIELD dielet: Performers will coordinate with the fabrication facility to fully test and characterize SHIELD dielets, assuring full functional schmoo windows across process, voltage, and temperature for all of the structures on the dielet. Proposers should provide their qualification strategy for proving that the SHIELD dielet meets all required program specifications.

E. Technical Area 2 Responsibilities:

There is no Government Furnished Equipment (GFE) or intellectual property provided to performers in Technical Area 2. Performers are responsible for implementing the required logic, encryption algorithm, communication technology, passive sensor management, etc.in the required standards using their defined methodology.

III. Technical Area 3: SHIELD Deployment Phases 1, 2, 3 Performers in Technical Area 3 will develop the ability to place SHIELD dielets in component packaging, verifying that it does not compromise the performance or reliability of the host component or the SHIELD dielet. Performers will develop and exercise an exemplary concept of operation (CONOP) employing the SHIELD device in a real product.

Technical Area 3 is executed across Phases 1, 2 and 3 of the SHIELD Program, and may comprise the collaborative solutions of multiple performers. During Phase 1, the proposed fundamental dielet package insertion, attachment, or lamination techniques are developed, and desired parametrics for a technology reduction are determined. Also in Phase 1, the network communications and server backbone design is initiated. This environment is to serve simply as a representative demonstration of the SHIELD proof of concept, and is not intended to provide the final, fielded IT system for SHIELD. Phase 2 will establish practical techniques and tooling associated with reliable, effective precision association of the dielet to the host package. The development of the network environment is also continued in Phase 2.

In Phase 3, these techniques are collectively deployed to demonstrate the SHIELD concept in an actual DoD product acquisition program.

A. Technical Area 3/Phase 1: Fundamental Package Technology, and proof-of-concept network protocol developments Months 1-18 During Phase 1 of Technical Area 3, performers will create a new technology for binding SHIELD authentication dielets to their host components. During this phase, the performer’s proposed new techniques for inserting, laminating, or attaching thinned dielets to the package will be developed and validated for their conformity to SHIELD program goals. At the close of Technical Area 3/Phase 1, performers will be prepared to begin fabrication of the tooling which demonstrates the secure and precise association of the dielet with the host component.

Also initiated in Technical Area 3/Phase 1 is the design of the network and security backbone upon which the proof-of-concept SHIELD demonstration will be conducted in Technical Area 3/Phase 3. Performers will develop the rudimentary network and conventions necessary to allow the SHIELD CONOP to be exercised as a proof-of-concept, conducting encrypted authentication between the inductive/RF appliance and the secure server. A strong emphasis is placed on requiring the use of open standards;

developing universal trust in the SHIELD concept is critical to its wider embrace. For Communication, Security, and Cryptography, only NIST, IEEE, and industry standards and protocols, and CMVP-verified code will be used in the design and in the exercise.

Performers will be asked to highlight specific areas where applicable standards did not formerly exist, for which SHIELD may establish new standards and industry conventions going forward. While SHIELD is a program to specifically develop a supply chain hardware root-of-trust, its exercise will establish exemplary, preferred operational conventions, and must be done with an eye towards future wide use and acceptance.

Technical Area 3 Performers will also develop an inexpensive inductive/RF appliance for use in executing the SHIELD concept. The appliance may be the retrofit or repurposing of an existing appliance such as a smartphone, with the addition of a probe that is plugged into the device.

B. Technical Area 3/Phase 1 Tasks:

1. Develop package placement target parametrics: Performers will develop the required specifications and their tolerances for dielet placement in the host package needed for acceptable SHIELD dielet functionality. An actual product package will be specified and provided by DARPA. The following parameters and concepts to be established or developed in Phase 1:

a. An understanding of the required coupling necessary to achieve sufficient inductive or RF power transfer and communication between the inductive/RF appliance and the SHIELD dielet. The SHIELD dielet is approximately 1 mm below the outer surface and the inductive/RF coupling should be active during the approximately 2 second transaction;

b. Acceptable depth tolerance of SHIELD dielet below surface of package, and insertion techniques achieving these tolerances;

c. Standardized positioning conventions that accommodate various package types.

Positioning conventions will also guide the alignment of the inductive/RF appliance to the location on the package where the SHIELD dielet can be exercised for a response, both in handheld as well as automated interrogation; and

d. Alternative dielet attachment conventions, test strategies and authentication procedures for accommodating host components which have heat sinks fully integrated into their packages. The demonstration CONOP to be exercised in the SHIELD program will use a component which does not have an integrated heat sink, however.

2. Create SHIELD dummy dielet surrogate: A selected Technical Area 3/Phase 1 performer will create a dummy dielet vehicle for use in exploring tooling and techniques for the actual SHIELD dielet when it becomes available. The dummy dielet will be designed and created by Technical Area 3/Phase 1 performers in conjunction with Technical Area 2 developers so that it closely resembles the form-factor of the anticipated end product in size and thickness. Simple electrical structures may be placed on the dummy dielet to assess specific issues of concern to developers.

The dummy dielet that is produced will be made available to other performers in the program as well, for their use in developing their own specific solutions.

3. Assure the reliability of the host component after SHIELD insertion: Starting with a base set of assumptions on the general SHIELD dielet size, thickness, electrical operation, and temperature specs, performers will assess potential impacts or changes to the reliability and serviceability of the host chip caused by the SHIELD dielet’s presence and operation within the host package. Potential concerns may include:

a. Packaging strain induced by the insertion operation or by the presence of the dielet in the package. Strain may compromise the host component reliability or modulate its device transconductance;

b. Hermetic seal failures in the host package caused by the dielet insertion or presence. Seal failures can potentially lead to corrosion within the IC;

c. High electromagnetic field impacts to the underlying component when the SHIELD dielet is interrogated by a manual or automated authentication inductive/RF probe. High fields potentially lead to dielectric breakdown, charging, or host component logic errors.

A substantial number of functional, packaged exemplary host components will be provided by DARPA to Technical Area 3 performers, along with design documentation describing underlying circuitry and process. This documentation and the parts may be used to model and test impacts the SHIELD CONOP may have on the underlying design. From this analysis, performers will be expected to derive rules on generic impacts that these physical and electromagnetic intrusions may have on any given electronic part based on its process and design features, and from that develop a suite of preferred specs for prudent dielet placement and operation in the package which will insure problem free, robust practice.

4. Assure the reliability of the SHIELD dielet in the host package placement: Performers will assure the integrity and reliability of the placed SHIELD dielet in the host package, considering potential damage caused by:

a. Chemical, mechanical, temperature, or electrically-induced materials interactions with the host packaging materials or process occurring during normal processing, packaging, dielet insertion or due to aging in normal use.

b. Chemical, mechanical, temperature, or electrically induced materials failures which should intentionally occur if the product is tampered with, and which must also be demonstrated to occur reliably and predictably.

c. Mechanical strain, compressive or tensile effects induced on the SHIELD dielet by the package or on the host component by the SHIELD dielet. Both static and dynamic changes should be studied, including: at-use temperature effects caused by differences in thermal expansion coefficients of the dielet and the package, forces placed on component during socket insertion or board assembly, and strain induced electrical behavior…