DARPA-BAA-12-53_Upside_Final For Posting_14Aug2012.pdf

Broad Agency Announcement

Unconventional Processing of Signals for Intelligent Data Exploitation

(UPSIDE)

Microsystems Technology Office

DARPA-BAA-12-53

August 14, 2012

Table of Contents

Part I: Overview Information Part II: Full Text of Announcement

Sec. I: FUNDING OPPORTUNITY DESCRIPTION A. Background:

B. Program Description C. Tasks D. Metrics E. Task 1: UPSIDE Computational Model

1. Task 1a: Inference Module

2. Task 1b: Image Processing Pipeline Demonstration Application:

3. Task 1c (option): Multi-Sensor Data Fusion Demonstration Application

F. Task 2: Mixed Signal (MS) CMOS Implementation Inference Processors

1. Task 2: Phase 1

2. Task 2: Phase 2

G. Task 3: Emerging Nanoscale Devices

1. Task 3: Phase 1

2. Task 3: Phase 2

H. Summary – Program Structure and Deliverables Sec II. AWARD INFORMATION Sec. III: ELIGIBILITY INFORMATION

A. Eligible Applicants B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and Organizational Conflicts of Interest C. Cost Sharing/Matching D. Other Eligibility Criteria

Sec. IV: APPLICATION AND SUBMISSION INFORMATION A. Address to Request Application Package B. Content and Form of Application Submission

1. Security and Proprietary Issues

2. Proposal Submission Information

3. For Proposers Requesting an Assistance Instrument:

4. For Proposers Requesting a Contract or Other Transaction Award Instrument

5. For All Proposers:

C. Full Proposal Format D. Submission Dates and Times

1. Full Proposal Date

2. Intergovernmental Review

3. Funding Restrictions

4. Other Submission Requirements

Sec. V: APPLICATION REVIEW INFORMATION A. Evaluation Criteria B. Review and Selection Process

Sec. VI: AWARD ADMINISTRATION INFORMATION A. Selection Notices

B. Administrative and National Policy Requirements

1. Meeting and Travel Requirements

2. Human Use

3. Animal Use

4. Publication Approval

5. Export Control

6. Subcontracting

7. Electronic and Information Technology

8. Employment Eligibility Verification

9. Additional Requirement and Responsibilities relating to Alleged Crimes by or against Contractor Personnel in Iraq and Afghanistan

10. Central Contractor Registration (CCR) and Universal Identifier Requirements ... 36

11. Reporting Executive Compensation and First-Tier Subcontract Awards

12. Updates of Information Regarding Responsibility Matters

13. Representation by Corporations Regarding Unpaid Delinquent Tax Liability or a Felony Conviction Under Any Federal Law

14. Cost Accounting Standards Notices and Certification Deviation 2012-00003 (Jan 2012)

15. Controlled Unclassified Information on Non-DoD Information Systems

C. Reporting D. Electronic Systems

1. Representations and Certifications

2. Wide Area Work Flow (WAWF)

3. i-Edison

Sec. VII: AGENCY CONTACTS Sec. VIII: OTHER INFORMATION

A. Intellectual Property Procurement Contract Proposers

1. Noncommercial Items (Technical Data and Computer Software)

2. Commercial Items (Technical Data and Computer Software)

B. Non-Procurement Contract Proposers – Noncommercial and Commercial Items (Technical Data and Computer Software) C. All Proposers – Patents D. All Proposers – Intellectual Property Representations E. Other Transactions (OTs):

F. Proposer’s Day……………………………...………………………………………..42

Part I: Overview Information

Federal Agency Name – Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO)

Funding Opportunity Title – Unconventional Processing of Signals for Intelligent Data Exploitation (UPSIDE)

Announcement Type – Initial Broad Agency Announcement Funding Opportunity Number – DARPA-BAA-12-53 Catalog of Federal Domestic Assistance Numbers (CFDA) – Not applicable.

Dates o Posting Date: August 14, 2012 o Proposer’s Day: September 10, 2012 in Arlington, VA o Proposal Due Date: October 12, 2012 o Estimated period of performance start: March 2013

Concise description of the funding opportunity: The UPSIDE program proposes an approach to compute-intensive data analysis using unconventional computation and data representations mapped to emerging new device technologies. By computing high level functions directly using the physics of the devices, we can expect orders of magnitude improvements in the power efficiency of these computations. Target applications include image sensor data analysis.

Anticipated individual awards – Multiple awards are anticipated.

Anticipated funding type - 6.1 Types of instruments that may be awarded – Procurement contract, grant, cooperative agreement or other transaction.

Any cost sharing requirements – None.

Agency contact o Dr. Dan Hammerstrom, Program Manager BAA Coordinator: DARPA-BAA-12-53@darpa.mil

DARPA/MTO

ATTN: DARPA-BAA-12-53

675 North Randolph Street Arlington, VA 22203-2114

PROPOSERS ARE CAUTIONED THAT EVALUATION RATINGS MAY BE LOWERED

AND/OR PROPOSALS REJECTED IF PROPOSAL PREPARATION (PROPOSAL FORMAT,

CONTENT, ETC.) AND/OR SUBMITTAL INSTRUCTIONS ARE NOT FOLLOWED.

THOSE INTENDING TO SUBMIT A PROPOSAL FOR AN ASSISTANCE INSTRUMENT

(GRANT OR COOPERATIVE AGREEMENT) ARE STRONGLY ENCOURAGED TO READ

THE INSTRUCTIONS PROVIDED AT SECTION IV(B)(4) REGARDING THE TIME

REQUIRED TO RECEIVE VALIDATION OF SUBMISSIONS MADE THROUGH

GRANTS.GOV. PROPOSALS THAT ARE VALIDATED AFTER THE PROPOSAL DUE

DATE/TIME WILL BE CONSIDERED LATE AND, AS SUCH, WILL NOT BE REVIEWED.

Part II: Full Text of Announcement

Sec. I: FUNDING OPPORTUNITY DESCRIPTION

The Defense Advanced Research Projects Agency often selects its research efforts through the Broad Agency Announcement (BAA) process. The BAA will appear first on the FedBizOpps website, http://www.fedbizopps.gov/, and Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA.

Proposed R&D activity will involve, but is not limited to:

Inference and pattern recognition Emerging devices Target recognition and tracking Image processing Self-organization Sparse data representation Simulation Mixed-signal CMOS Sensor data processing

Proposed research should investigate innovative approaches that enable revolutionary advances in science, devices, and/or systems. Specifically excluded is research that results primarily in evolutionary improvements to the existing state of practice.

A. Background:

The DoD has become increasingly reliant on Intelligence, Surveillance and Reconnaissance (ISR) applications to accomplish their mission. Currently there is a pressing need to dramatically expand the DoD’s capabilities into the real-time processing of wide-area, high-resolution video imagery, with systems performing target recognition and tracking over large numbers of objects. Not only is the volume of sensor data increasing exponentially, there is also a dramatic increase in the complexity of analysis, reflected in the number of operations per pixel per second. These expanding processing requirements for ISR missions, as well as other DoD sensor applications, are quickly outpacing the capabilities of existing and projected computing platforms.

Traditionally, Moore’s Law has enabled a steady progression of low-cost, high performance digital computing hardware, providing the processing power needed to keep up with the DoD’s mission-based system requirements. But Moore’s law is beginning to stall, especially in power efficiency, significantly impacting the projected computation capabilities of portable platforms.

In order for the U.S. to maintain technological superiority over its adversaries, the DoD seeks to develop alternative, non-Boolean, non-CMOS, computing approaches to break through the digital CMOS computational efficiency barrier that is limiting the ultimate performance of embedded digital computing hardware.

B. Program Description

DARPA is soliciting innovative research proposals for the Unconventional Processing of Signals for Intelligent Data Exploitation (UPSIDE) program that will address the open problems facing real-time ISR systems and other power-constrained applications. The objective of the UPSIDE program is to create a high-level non-Boolean computational model and map it directly to the unique operational properties of new, power efficient, non-CMOS, nanoscale devices. UPSIDE will achieve significant increases in power efficiency and performance on an important class of sensor data and image analysis applications that identify and track large numbers of targets.

The UPSIDE program will result in a new generation of computing structures based on revolutionary advances in ISR processing, particularly for DoD applications requiring embedded, real-time sensor data analysis. Because Boolean data representations are inherently power-inefficient for many datasets, particularly those produced by noisy, analog, real-time sensors, the UPSIDE program aims to establish an unconventional, non-Boolean computing paradigm, that will enable new and needed capabilities in the area of sensor data analysis.

To this end, the UPSIDE program will drive the development of a synergistic approach to computing based on probabilistic computational models, sparse data structures, self-organizing systems, and new device technologies that will emerge (“emerging devices” in this BAA) to become alternatives to today's commercial CMOS FETs. The goal is to develop a computing infrastructure and functional implementations that demonstrate three orders of magnitude improvement in processing speed, and four orders of magnitude improvement in power efficiency. These gains will constitute a new and disruptive level of embedded computational efficiency for future real-time sensor systems.

Inference is the fundamental computational model of the UPSIDE program. An “Inference Module” (IM) is a specific implementation of the computational model. We expect this module to have the following characteristics:

1. A probabilistic inference based model that leverages energy minimization.

2. Systems organized into multiple levels of abstraction, where each level consists of self-organizing (adapting) devices.

3. Data represented in a sparse distributed form, mapping efficiently to collections of non-digital computing devices.

4. The capability to handle both spatial and temporal data, for target tracking and processing of other time-based information.

The IM is loosely defined in this BAA to allow the proposers some freedom in crafting their model.

Formally, one can think of the entire image analysis hierarchy as a Bayesian network, where the sensor input is the evidence and the inference process determines the probability distribution of the output to find the object that is the most likely interpretation of the input presented to the network. A simple definition of inference is a weighted pattern match of its inputs against a set of internal patterns. Such matching requires the existence of a suitable metric over the vector space as well as estimates of conditional and prior probabilities (beliefs). For many systems, feedback from higher levels can also be provided as part of the inference process. IMs developed by the use of “Deep Learning” procedures, for example, fit the general notion of inference as defined here.

Instead of being programmed, each IM is expected to self-organize, adapting to its inputs. Self-organization, as defined by this BAA, is the process of learning the internal patterns based on the statistics of the input and certain key parameters. Generally, the conditional and prior probabilities are approximated by statistics collected about the inputs. By restricting the number of internal patterns or hidden layer dimensions, a kind of maximum entropy data-reduction is performed. Self-organization should be possible in real-time during system operation. Self-organization should be controllable, since some modules may have their representations provided a priori. Other modules may never need to adapt after an initial learning phase, or may continue to adapt during system operation.

There is an additional requirement that the data representations used by the IMs be sparsely distributed. There are a variety of ways to develop sparsely distributed vectors and proposers are free to use any technique that fits the hardware architectures they are developing. The purpose of this requirement is to ease the implementation of the IMs in mixed signal CMOS and emerging devices.

C. Tasks

The UPSIDE program consists of an interdisciplinary approach which has three mandatory tasks performed over two phases. Proposers must address all three tasks.

Task 1 forms the foundation for the program and involves the development of the computational model as well as the image processing application that will be used for demonstration and benchmarking. Tasks 2 and 3 build upon the results of Task 1 to demonstrate the IM implemented in mixed signal CMOS in Task 2, and with non-CMOS emerging devices in Task

3. The ability to successfully address all three tasks will require close collaboration within the proposer’s team, and will be an important aspect of any successful UPSIDE effort.

Phase 1 will focus primarily on system feasibility by building a sophisticated imaging application using a proposer defined IM. The proposer will start with an imaging application involving object recognition and tracking in a large visual space. There should be a simulation of this application based on traditional image processing techniques. The proposer will then implement a software version of the application making extensive use of the IM computational model. The proposer should benchmark this IM based implementation, known as the “Gold” implementation, against the conventional implementation, to assess recognition accuracy. The Gold implementation will form the core technology that the hardware implementations developed in Tasks 2 and 3 will be based on and measured against.

Phase 2 will focus on benchmarking software and hardware implementations of the IM, including a system test bed implementation of the IM in mixed signal CMOS.

D. Metrics

All of the UPSIDE tasks require benchmarking against the Gold model developed in Task 1. It is the goal of the UPSIDE program to develop computational techniques that show many orders of magnitude improvement in speed and power without any critical loss in accuracy. For this benchmarking there are three general system metrics that will be measured: speed or throughput, power efficiency, and accuracy. It should be possible to derive these metrics from performance data provided by the various simulations. Proposers should specify in the proposal, in detail, the metrics that will be used to measure improvements realized in the UPSIDE program.

The metrics are intended to measure the value and general progress of the proposer’s approach and therefore the proposer is free to define these metrics, as well as any other additional metrics they may identify. The metrics defined by the proposer should be consistent with standard industry usage and with the UPSIDE program goals of delivering three orders of magnitude in increased performance, and four orders of magnitude reduction in power consumption, without critical loss of accuracy.

E. Task 1: UPSIDE Computational Model

1. Task 1a: Inference Module

Task 1a involves the development of the probabilistic computation model for the UPSIDE program as discussed above. The IM is the primary building block for the required object recognition and tracking application. The chief aim of this task is to develop the basic IM abstraction, sparse data representation and self-organization capability necessary to form a complete, high-level, functional framework that can be used to re-implement a full-scale imaging application based on the IM abstraction. The IM is the centerpiece of the program.

2. Task 1b: Image Processing Pipeline Demonstration Application:

Task 1b involves the development of the application driver for the UPSIDE technology. In most imaging applications, a series of transformations and analyses are applied to an image. These may start with filters that operate directly on image sensor data, followed by several stages of feature extraction for increasingly complex features. Together, the series of linked components that perform these operations and analyses is called a pipeline. Unlike a conventional pipeline, in the pipeline defined here, latter stages of the pipeline may feed information, such as upper level hypotheses or regions of interest, back to earlier stages. Performance on the UPSIDE program requires an Image Processing Pipeline (IPP) application that can identify and track stationary and moving objects. It is assumed that the performer will have access to a conventional implementation of an IPP that will serve as a baseline benchmark. Performers will also be required to provide the necessary data to adequately exercise the pipeline.

Near the end of the pipeline, it is likely that there will be some knowledge or contextual processing. Since one of the goals of the UPSIDE program is to explore unconventional computing for the entire pipeline, it is expected that proposers will also use the IM as much as possible for back end processing.

3. Task 1c (option): Multi-Sensor Data Fusion Demonstration Application

Proposers are encouraged to show the general applicability of the IM developed in Task 1a beyond the IPP, by using it in a second application performing sensor fusion and data analysis, or in some other relevant sensor data analysis system of interest to the DoD. One example might be a Tactical Remote Sensor (TRS) system. TRS systems collect data from large numbers of geographically dispersed sensors for detection and recognition, providing real-time situational awareness. The sensor modalities investigated may include seismic, acoustic, magnetic, imaging (thermal and electro-optical), radio frequency, ultra-wide band, and electromagnetic. The approach for this task should be similar to Task 1b. Again it is assumed that the performer will have access to a conventional implementation of the sensor application and the necessary data to adequately exercise the pipelines, thereby demonstrating the improvement in speed and power efficiency, with comparable accuracy, based on the UPSIDE approach. This task will be performed during Phase 2 and need not be a part of any of the hardware demonstrations in Tasks 2 and 3.

Phase 1 Task 1a: Required Program Elements

Definition and simulation of Inference Module (IM).

Phase 1 Task 1b: Required Program Elements

Definition of the Gold IPP simulation for video data supporting a DoD relevant image application involving target recognition and tracking.

Software simulations of the IPP in the following forms:

o Conventional object recognition and tracking of images.

o An implementation of the Gold IPP using the IM as the fundamental building block.

Benchmark the accuracy of the Gold IPP against a conventional implementation of the original IPP using still images and short sequences of video data.

Phase 2 Task 1b: Required Program Elements Port the IPP simulator to a high performance computing system.

Benchmark IPP simulations using longer, more complex object tracking sequences of higher definition video data.

Phase 2 Task 1c: Optional Program Element

Definition of Tactical Remote Sensor (TRS) pipeline for sensor data supporting a DoD relevant TRS application or other sensor system of interest.

Software simulations of TRS system (or other sensor system of interest).

Analyze performance, power, and accuracy of the IM based TRS system.

F. Task 2: Mixed Signal (MS) CMOS Implementation Inference Processors

The primary focus of Task 2 is to produce a MS CMOS implementation of the IM developed in Task 1. The goal of the MS CMOS IM implementation is to demonstrate that the computational model developed under Task 1 has considerable advantages over conventional Boolean approaches, even when implemented in traditional hardware. Although the power and performance benefit of the UPSIDE approach will be fully realized through the combination of the emerging devices (Task 3) with the computational model (Task 1), it is expected that there will be a substantial power and performance benefit gained from implementing the UPSIDE non- Boolean computational model in MS CMOS. Development of a MS CMOS IM and system testbed will also allow the concepts developed in Task 1 to be implemented in a proven technology, thus verifying the viability of the performer’s specific approach prior to implementation with emerging device technology. The MS CMOS IM may also result in a useful interim technology for real DoD applications.

1. Task 2: Phase 1

In Phase 1, a MS CMOS IM chip will be designed and fabricated. The MS CMOS IM chip will normally consist of multiple IMs. The output for this task will be both a hardware level description and a simulation of the design, as well as a fabricated, packaged and tested chip produced in a state of the art MS CMOS process. The MS CMOS IM design should implement all of the necessary inference characteristics modeled in Task 1, and include any necessary circuitry for I/O and control. Proposers have the freedom to utilize digital logic and conventional computation for control and data communication.

Also in this task, a version of the IPP will be developed where the IM components in the pipeline simulate the CMOS IM operation specifications, factoring into the IPP the degree to which the MS CMOS approximates the ideal IM defined in Task 1a. The simulation should account for the data movement and transformations through the MS CMOS IM chips used throughout the IPP.

The simulated version of the IPP will be used to validate results of the hardware version in Phase

2. Validation and benchmarking of the simulated MS CMOS IM IPP will be performed to compare the performance, power consumption, and accuracy results against the conventional, non-IM based IPP.

2. Task 2: Phase 2

In Phase 2 performers will demonstrate the functionality of the MS CMOS IM chip in an IPP testbed that is a hardware implementation of the MS CMOS IPP simulation. The hardware testbed will be validated against the simulations developed in Phase 1. The testbed will be used to prove the capability of the UPSIDE approach by self-organizing to a set of training images with the subsequent processing of image sensor data in real-time. Improvements in performance and power efficiency will be measured. The requirements for moving to a commercial version of the MS CMOS chip, including an estimate of the expected performance/power will be provided as a report.

Phase 1: Task 2 Required Program Elements An implementation of IPP simulation using a simulation of the MS CMOS IM chip.

o Obtain estimates of system performance, power requirements, data precision, and accuracy.

The design of a MS CMOS IM implementation.

o Develop IM digital control and communication circuitry.

Fabricate, package and test the MS CMOS IM chip.

o Verify performance, power, and accuracy.

Phase 2: Task 2 Required Program Elements

Develop a hardware IPP testbed system based on the MS CMOS IM chip fabricated in Phase 1.

Validate and benchmark system testbed.

Report on requirements for commercialization of MS CMOS IM chip.

G. Task 3: Emerging Nanoscale Devices

The biggest impact on speed and power efficiency delivered by the UPSIDE program, will result from leveraging the physics of new and emerging nanoscale devices for the implementation of the UPSIDE IM. Designing and fabricating circuits based on such devices is the focus of the third task. Circuits will be produced from emerging devices to demonstrate the device’s ability to perform the basic IM computation. Emerging device circuit measurements will provide the basis for a realistic IM simulation, showing the expected orders of magnitude gains in performance and power efficiency.

Though new devices have been under investigation for some time as potential replacements for digital CMOS, most efforts have focused on demonstrating a digital switch. It may not be possible to create a commercial, integrated chip based on emerging devices within the time frame or scope of the UPSIDE program. However, building and demonstrating real IM circuits based on emerging devices (ED IM) will help prove their intrinsic benefits, which will lead to their eventual commercialization. The objective of Task 3, which is the culmination of the UPSIDE program, is to produce a functioning IM based on emerging devices with sufficient functionality that an implementation of the entire IPP is possible.

1. Task 3: Phase 1

Task 3 Phase 1 begins with the development of a non-CMOS, nanoscale emerging device. This development includes the fabrication and testing of simple emerging device circuits to evaluate the performance, power efficiency, and accuracy of the selected device(s). This development will help guide the design requirements of more complex circuits and the development of the full ED IM simulation. Proposers should explain how the physics of their emerging device(s) can be leveraged to perform within the UPSIDE computational IM and estimate the resulting IM’s prospective performance. Proposers need not be limited to a single candidate device.

Phase 1 will also develop an ED IM simulation of the behavior of circuits implemented using emerging devices. High level ED IM simulations that incorporate the functional properties of the emerging devices will be integrated into the IPP to produce a more realistic estimate of the performance benefits gained from the ED IM. The ED IM simulation should exhibit all the described properties of the UPSIDE compute model, including spatial and temporal inference, self-organization, and sparse data representation.

Finally, Phase 1 will develop any I/O and control circuitry required to operate a hardware implementation of the ED IM. In order to test and demonstrate the ED IM, a digital interface is needed. The I/O and control circuitry to perform this function will be designed and tested during Phase 1 in anticipation of the IPP demo in Phase 2. An objective of the program is to fabricate the devices directly on a CMOS substrate as a precursor to a commercial emerging-device-based product. Such an approach would require the development of a custom CMOS chip for the ED IM implementation. While such direct CMOS fabrication is desirable for Task 3, it is not required; however, some mechanism for controlling and communicating with the ED IM during testing is required.

2. Task 3: Phase 2

In Phase 2, the ED IM simulated version of the IPP will be used to compare its accuracy and performance against the Gold version built in Task 1. The ED IM simulated IPP should accurately reflect the emerging device behavior. The ED IM based IPP simulation will be tested with the same image/video data used to validate the Gold version, to benchmark the estimated power savings, increased performance gains, and accuracy of the ED IM. The ED IM version of the IPP should be instrumented to allow the simulation of static and dynamic faults and errors.

An estimate of possible ED IM implementation yield should be factored into the simulation to determine whether fault or error correction, beyond that provided by the basic IM algorithms, is required.

Also in Phase 2, a physical ED IM will be fabricated and integrated with the control circuitry designed in Phase 1. The accuracy of the hardware ED IM will be validated against the simulated version of the ED IM. The power and performance of the hardware ED IM will also be determined.

A detailed written analysis of the performance, power efficiency, system accuracy and yield of an ED IM implementation of the entire IPP is required. In addition, any remaining problems, including those of fabrication, yield, operating parameters and system integration, that will need to be solved for commercial realization of an IM IPP based on emerging devices, should be included as well as potential solutions to those problems.

Phase 1: Task 3 Required Program Elements Develop emerging device technology including demonstration of simple circuits.

Develop a software simulation of the ED IM and insert into the IPP.

Develop test, I/O and control circuitry for the ED IM.

Phase 2: Task 3 Required Program Elements Benchmark the software version of IPP based on the ED IM models against the Gold simulation.

Add a fault simulation capability to the ED IM IPP and demonstrate operation over a reasonable set of yield assumptions.

Fabrication of ED IM, and integration with the test, I/O and control circuitry.

Benchmark the physical realization of ED IM against the ED IM simulation.

Report describing technical challenges for commercialization of an ED IM based IPP system.

H. Summary – Program Structure and Deliverables

Phase 1 = up to 30 months.

Phase 2 = 21 months.

Total program not to exceed 51 months.

Table 1: UPSIDE Technology Development

Computational Model and Application Development

Task Milestones and Deliverables

Task 1 – Phase 1 Definition and simulation of IM.

Definition of the IPP and “Gold” software simulation.

Benchmark the Gold IPP against conventional implementation.

Task 1 – Phase 2 Port the IPP simulator to a high performance computing system.

Benchmark the Gold IPP using more complex data.

Optional Task 1c - Phase 2 Benchmark of the non-IM against the IM based TRS system.

Mixed Signal CMOS IM Implementation

Task Milestones and Deliverables

Task 2 – Phase 1 Implement the IPP based on a simulation of the CMOS IM chip.

Design the MS CMOS IM chip.

Fabricate, package and test the MS CMOS IM chip.

Task 2 – Phase 2 Develop a hardware IPP testbed system based on the MS CMOS IM chip fabricated in Phase 1.

Validate and benchmark the system testbed.

Report on requirements for commercialization of MS CMOS IM chip.

Emerging / Nanoscale Devices Implementation

Task Milestones and Deliverables

Task 3 – Phase 1 Develop emerging device technology and demonstrate simple circuits.

Develop a software simulation of the ED IM and insert into the IPP.

Develop test, I/O and control circuitry for the ED IM.

Task 3 – Phase 2 Benchmark the software version of ED IM IPP.

Fabricate ED IM, and integrate with the test, I/O and control circuitry.

Benchmark the physical realization of ED IM against the ED IM simulation.

Report describing technical challenges to commercialization of an ED IM based IPP system.

Table 2: UPSIDE Schedule

It is anticipated that four principal investigator (PI) meetings will be held each year for each performer at roughly three month intervals, with the first PI meeting occurring at program initiation. Difficulties encountered and possible solutions will be discussed. The goals of the PI meetings will be to: (a) review program activities and overall program progress; (b) review innovations / accomplishments; (c) coordinate system test and simulation activities; and (d) plan for the next three month period. The locations for these program reviews, coordination and technical interchanges, PI meetings, and other events will be specified by the Government. In general, for budgeting travel, assume the locations of any detailed performer program reviews will be held at the performer’s location. In addition, the government may want to conduct monthly teleconferences to assess program status.

There will also be two UPSIDE Program conferences for all the performers prior to the end of each phase. For planning purposes these two meetings will be held alternately at east and west coast locations. Additional meetings may be necessary if important issues arise between planned program meetings.

Sec II. AWARD INFORMATION

Multiple awards are anticipated. The amount of resources made available under this BAA will depend on the quality of the proposals received and the availability of funds.

The Government reserves the right to select for negotiation all, some, one, or none of the proposals received in response to this solicitation, and to make awards without discussions with proposers. The Government also reserves the right to conduct discussions if it is later determined to be necessary. If warranted, portions of resulting awards may be segregated into pre-priced options. Additionally, DARPA reserves the right to accept proposals in their entirety or to select only portions of proposals for award. In the event that DARPA desires to award only portions of a proposal, negotiations may be opened with that proposer. The Government reserves the right to fund proposals in Phases with options for continued work at the end of one or more of the Phases.

Awards under this BAA will be made to proposers on the basis of the evaluation criteria listed below (see section labeled “Application Review Information”, Sec. V.), and program balance to provide overall value to the Government. Proposals identified for negotiation may result in a procurement contract, grant, cooperative agreement, or other transaction depending upon the nature of the work proposed, the required degree of interaction between parties, and other factors. The Government reserves the right to request any additional, necessary documentation once it makes the award instrument determination. Such additional information may include but is not limited to Representations and Certifications. The Government reserves the right to remove proposers from award consideration should the parties fail to reach agreement on award terms, conditions and cost/price within a reasonable time or the proposer fails to timely provide requested additional information.

As of the date of publication of this BAA, DARPA expects that program goals for this BAA may be met by proposers intending to perform 'fundamental research,' i.e., basic or applied research performed on campus in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization the results of which ordinarily are restricted for proprietary or national security reasons. Notwithstanding this statement of expectation, DARPA is not prohibited from considering and selecting research proposals that, while perhaps not qualifying as 'fundamental research' under the foregoing definition, still meet the BAA criteria for submissions. If proposals are selected for award that offer other than a fundamental research solution, then DARPA will either work with the proposer to modify the proposed statement of work to bring the research back into line with fundamental research or else the proposer will agree to restrictions in order to receive an award. See Section VI.B.4 for further information on fundamental, non-fundamental and restricted research. In all cases, the DARPA contracting officer shall have sole discretion to select award instrument type and to negotiate all instrument provisions with selectees.

Sec. III: ELIGIBILITY INFORMATION

A. Eligible Applicants

All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA. Historically Black Colleges and Universities (HBCUs), Small Businesses, Small Disadvantaged Businesses and Minority Institutions (MIs) are encouraged to submit proposals and join others in submitting proposals; however, no portion of this announcement will be set aside for these organizations’ participation due to the impracticality of reserving discrete or severable areas of this research for exclusive competition among these entities.

Federally Funded Research and Development Centers (FFRDCs) and Government entities (Government/National laboratories, military educational institutions, etc.) are subject to applicable direct competition limitations and cannot propose to this BAA in any capacity unless they address the following conditions. FFRDCs must clearly demonstrate that the proposed work is not otherwise available from the private sector AND must also provide a letter on letterhead from their sponsoring organization citing the specific authority establishing their eligibility to propose to government solicitations and compete with industry, and compliance with the associated FFRDC sponsor agreement and terms and conditions. This information is required for FFRDCs proposing to be prime or subcontractors. Government entities must clearly demonstrate that the work is not otherwise available from the private sector and provide written documentation citing the specific statutory authority (as well as, where relevant, contractual authority) establishing their ability to propose to Government solicitations. At the present time, DARPA does not consider 15 U.S.C. 3710a to be sufficient legal authority to show eligibility.

While 10 U.S.C. 2539b may be the appropriate statutory starting point for some entities, specific supporting regulatory guidance, together with evidence of agency approval, will still be required to fully establish eligibility. DARPA will consider eligibility submissions on a case-by-case basis; however, the burden to prove eligibility for all team members rests solely with the Proposer.

B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and Organizational Conflicts of Interest

Current federal employees are prohibited from participating in particular matters involving conflicting financial, employment, and representational interests (18 USC 203, 205, and 208).

The DARPA Program Manager for this BAA is Dr. Dan Hammerstrom. Once the proposals have been received, and prior to the start of proposal evaluations, the Government will assess potential conflicts of interest and will promptly notify the Proposer if any appear to exist.

(Please note, the Government assessment does NOT affect, offset, or mitigate the Proposer’s own duty to give full notice and planned mitigation for all potential organizational conflicts, as discussed below.)

Without prior approval or a waiver from the DARPA Director, in accordance with FAR 9.503, a Contractor cannot simultaneously provide scientific, engineering, technical assistance (SETA) or similar support and also be a technical performer. Therefore, all Proposers as well as proposed subcontractors and consultants must affirm whether they (their organizations and individual team members) are providing SETA or similar support to any DARPA technical office(s) through an active contract or subcontract. All affirmations must state which office(s) the Proposer, subcontractor, consultant, or individual supports and identify the prime contract number(s).

Affirmations shall be furnished at the time of proposal submission. All facts relevant to the existence or potential existence of organizational conflicts of interest (FAR 9.5) must be disclosed. The disclosure must include a description of the action the Proposer has taken or proposes to take to avoid, neutralize, or mitigate such conflict. If in the sole opinion of the

Government after full consideration of the circumstances, a proposal fails to fully disclose potential conflicts of interest and/or any identified conflict situation cannot be effectively mitigated, the proposal will be rejected without technical evaluation and withdrawn from further consideration for award.

If a prospective Proposer believes that any conflict of interest exists or may exist (whether organizational or otherwise) or has questions on what constitutes a conflict of interest, the Proposer should promptly raise the issue with DARPA by sending his/her contact information and a summary of the potential conflict to the BAA mailbox (DARPA-BAA-12-53@dapra.mil) before time and effort are expended in preparing a proposal and mitigation plan.

C. Cost Sharing/Matching

Cost sharing is not required for this particular program; however, cost sharing will be carefully considered where there is an applicable statutory condition relating to the selected funding instrument (e.g., for any Other Transactions under the authority of 10 U.S.C. § 2371). Cost sharing is encouraged where there is a reasonable probability of a potential commercial application related to the proposed research and development effort.

D. Other Eligibility Criteria

Collaborative efforts/teaming are encouraged.

Sec. IV: APPLICATION AND SUBMISSION INFORMATION

A. Address to Request Application Package

This solicitation contains all information required to submit a proposal. No additional forms, kits, or other materials are needed. This notice constitutes the total BAA. No additional information is available, nor will a formal Request for Proposal (RFP) or additional solicitation regarding this announcement be issued. Requests for same will be disregarded.

B. Content and Form of Application Submission

1. Security and Proprietary Issues

NOTE: If proposals are classified, the proposals must indicate the classification level of not only the proposal itself, but also the anticipated award document classification level.

The Government anticipates proposals submitted under this BAA will be unclassified. However, if a proposal is submitted as “Classified National Security Information” as defined by Executive Order 13526, then the information must be marked and protected as though classified at the appropriate classification level and then submitted to DARPA for a final classification determination.

Security classification guidance via a DD Form 254, “DoD Contract Security Classification Specification,” will not be provided at this time, since DARPA is soliciting ideas only. After reviewing the incoming proposals, if a determination is made that the award instrument may result in access to classified information, a DD Form 254 will be issued and attached as part of the award.

Proposers choosing to submit a classified proposal from other classified sources must first receive permission from the respective Original Classification Authority in order to use their information in replying to this BAA. Applicable classification guide(s) should also be submitted to ensure the proposal is protected at the appropriate classification level.

Classified submissions shall be appropriately and conspicuously marked with the proposed classification level and declassification date. Submissions requiring DARPA to make a final classification determination shall be marked as follows:

CLASSIFICATION DETERMINATION PENDING. Protect as though classified (insert the recommended classification level: (e.g., Top Secret, Secret or Confidential)

Classified submissions shall be in accordance with the following guidance:

Confidential and Secret Collateral Information: Use classification and marking guidance provided by previously issued security classification guides, the DoD Information Security Manual (DoDM 5200.01, Volumes 1 - 4) and the National Industrial Security Program Operating Manual (DoD 5220.22-M) when marking and transmitting information previously classified by another Original Classification Authority. Classified information at the Confidential and Secret level may be submitted via ONE of the two following methods:

1. Hand-carried by an appropriately cleared and authorized courier to the DARPA CDR. Prior to traveling, the courier shall contact the DARPA CDR at 703-526-4052 to coordinate arrival and delivery.

OR

2. Mailed via appropriate U.S. Postal Service methods (e.g., (USPS)

Registered Mail or USPS Express Mail). All classified information will be enclosed in opaque inner and outer covers and double wrapped. The inner envelope shall be sealed and plainly marked with the assigned classification and addresses of both sender and addressee.

The inner envelope shall be addressed to:

Defense Advanced Research Projects Agency ATTN: Microsystems Technology Office

Reference: (DARPA-BAA-12-53)

The outer envelope shall be sealed with no identification as to the classification of its contents and addressed to:

Defense Advanced Research Projects Agency Security & Intelligence Directorate, Attn: CDR

All Top Secret materials: Top Secret information should be hand carried by an appropriately cleared and authorized courier to the DARPA CDR. Prior to traveling, the courier shall contact the DARPA CDR at 703-526-4052 to coordinate arrival and delivery.

Special Access Program (SAP) Information: SAP information must be transmitted via approved methods. Prior to transmitting SAP information, contact the DARPA SAPCO at 703-526-4052 for instructions.

Sensitive Compartmented Information (SCI): SCI must be transmitted via approved methods. Prior to transmitting SCI, contact the DARPA Special Security Office (SSO) at 703- 526-4052 for instructions.

Proprietary Data: All proposals containing proprietary data should have the cover page and each page containing proprietary data clearly marked as containing proprietary data. It is the Proposer’s responsibility to clearly define to the Government what is considered proprietary data.

Proposers must have existing and in-place prior to execution of an award, approved capabilities (personnel and facilities) to perform research and development at the classification level they propose. It is the policy of DARPA to treat all proposals as competitive information, and to disclose their contents only for the purpose of evaluation. Proposals will not be returned. The original of each proposal received will be retained at DARPA and all other non-required copies destroyed. A certification of destruction may be requested, provided the formal request is received at this office within 5 days after unsuccessful notification.

2. Proposal Submission Information

Proposers are required to submit proposals by the time and date specified in the BAA in order to be considered during the single round of selections. Proposals received after the time and date specified in the BAA will be considered late and as such, will not be evaluated.

The typical proposal should express a consolidated effort in support of one or more related technical concepts or ideas. Disjointed efforts should not be included into a single proposal.

Restrictive notices notwithstanding, proposals may be handled, for administrative purposes only, by a support contractor. This support contractor is prohibited from competition in DARPA technical research and is bound by appropriate nondisclosure requirements. Proposals and abstracts may not be submitted by fax or e-mail; any so sent will be disregarded.

Proposals not meeting the format described in the BAA may not be reviewed.

3. For Proposers Requesting an Assistance Instrument:

Grant or cooperative agreement proposals may only be submitted to DARPA through Grants.gov or in hard-copy. Grant or cooperative agreement proposals may not be submitted through any other means (including T-FIMS and other comparable systems). If proposers intend to use Grants.gov as their means of submission, then they must submit their entire proposal through Grants.gov; applications cannot be submitted in part to Grants.gov and in part as a hard-copy.

Proposers using the Grants.gov APPLY do not submit paper proposals in addition to the Grants.gov APPLY electronic submission.

Proposers must complete the following steps in the order listed below before submitting proposals on Grants.gov (these steps are also detailed at www.grants.gov/applicants/get_registered.jsp):

Proposers must obtain a DUNS number Proposers must register their organization in the Central Contractor Registration (CCR) https://www.bpn.gov/ccr/default.aspx) Proposers must register the Authorized Organization Representative (AOR) in Grants.gov Proposers must have the organization’s E-BIZ point of contact authorize the AOR to submit applications.

Once Grants.gov has received a proposal submission, Grants.gov will send two email messages to advise proposers as to whether or not their proposals have been validated or rejected by the system; IT MAY TAKE UP TO TWO DAYS TO RECEIVE THESE EMAILS. The first email will confirm receipt of the proposal by the Grants.gov system; this email only confirms receipt, not acceptance, of the proposal. The second will indicate that the application has been successfully validated by the system prior to transmission to the grantor agency or has been rejected due to errors. If the proposal is validated, then the proposer has successfully submitted their proposal. If the proposal is rejected, the proposer will have to resubmit their proposal.

Once the proposal is retrieved by DARPA, the proposer will receive a third email from Grants.gov. To avoid missing deadlines, proposers should submit their proposals in advance of the final proposal due date with sufficient time to receive confirmations and correct any errors in the submission process through Grants.gov. For more information on submitting proposals to Grants.gov, visit the Grants.gov submissions page at:

http://grants.gov/applicants/apply_for_grants.jsp

Proposers electing to submit grant or cooperative agreement proposals via grants.gov must complete the SF 424 R&R form (Application for Federal Assistance, Research and Related) and the SF-LLL (if required). Please use the Attachments Form and upload, as two separate documents, Volume I, Technical and Management Proposal and Volume II, the Cost Proposal, as well as any other documents require by the BAA (i.e., subcontract proposals). No other

Grants.gov forms are required. Please note that Grants.gov does not accept zipped or encrypted documents uploaded at attachments. Please follow the document made available on grants.gov as part of the solicitation entitled “Instructions for Using Grants.gov to Apply for a Grant or Agreement from DARPA (Short Form),” dated 20 October 2011, for more information.

If submitting hard-copy, an original and (4) copies of the proposal and (4) electronic copies of the proposal on a CD-ROM shall be submitted to DARPA/MTO, via 675 North Randolph Street, Arlington VA 22203-2114 (Attn: DARPA-BAA-12-53), no later than time and date specified in Section IV.B.6 Submission Dates and Times.

Technical support for Grants.gov submissions may be reached at 1-800-518-4726 or support@grants.gov.

4. For Proposers Requesting a Contract or Other Transaction Award Instrument:

Proposals not requesting a grant or cooperative agreement sent in response to DARPA-BAA-12- 53 must be submitted through T-FIMS. See https://baat.