DARPA-BAA-12-13_Amendment No. 01_Final For Posting_11Nov11.pdf

Broad Agency Announcement Radio Frequency-Field Programmable Gate Arrays (RF-FPGA)

Microsystems Technology Office

DARPA-BAA-12-13

November 9, 2011 (Amendment No. 01 – As amended through 11 November 2011)

Table of Contents

Part I: Overview Information – p4 Part II: Full Text of Announcement – p5

Sec. I: FUNDING OPPORTUNITY DESCRIPTION – p4 Sec II. AWARD INFORMATION – p13 Sec. III: ELIGIBILITY INFORMATION – p14

A. Eligible Applicants – p14 B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and

Organizational Conflicts of Interest – p14 C. Cost Sharing/Matching – p15

Sec. IV: APPLICATION AND SUBMISSION INFORMATION – p15 A. Address to Request Application Package – p15 B. Content and Form of Application Submission – p16

Sec. V: APPLICATION REVIEW INFORMATION – p28 A. Evaluation Criteria – p28 B. Review and Selection Process – p29

Sec. VI: AWARD ADMINISTRATION INFORMATION – p30 A. Selection Notices – p30 B. Administrative and National Policy Requirements – p31 C. Reporting – p36 D. Electronic Systems – p36

Sec. VII: AGENCY CONTACTS – p36 Sec. VIII: OTHER INFORMATION – p37

A. Intellectual Property Procurement contract Proposers – p37 B. Non-Procurement Contract Proposers – Noncommercial and Commercial

Items – p38 C. All Proposers – Patents – p39 D. All Proposers – Intellectual Property Representations – p39 E. Other Transactions (OTs) – p39

Sec. IX: ATTACHMENTS

Part I: Overview Information

Color Legend:

• Federal Agency Name – Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO)

• Funding Opportunity Title – Radio Frequency-Field Programmable Gate Arrays (RF-

FPGA)

• Announcement Type – Initial Announcement.

• Funding Opportunity Number – DARPA-BAA-12-13

• Catalog of Federal Domestic Assistance Numbers (CFDA) – Not applicable.

• Dates o Posting Date: 9 November 2011 o Abstract Due Date: 7 December 2011 o Proposal Due Date: 26 January 2012

• Concise description of the funding opportunity – The goal of RF-FPGA is to develop field-programmable, fully adaptable, and waveform agnostic integrated RF front-ends and associated design tools for next-generation military cognitive communications, radar and electronic warfare platforms.

• Anticipated individual awards – Multiple awards are anticipated.

• Types of instruments that may be awarded – Procurement contract, grant, cooperative agreement or other transaction.

• Any cost sharing requirements – None.

• Agency contact o Dr. William J. Chappell

DARPA/MTO

ATTN: DARPA-BAA-12-13

3701 North Fairfax Drive Arlington, VA 22203-1714

FAX: 703-807-9965

PHONE: 571-218-4507

EMAIL: William.Chappell@darpa.mil

BAA Coordinator: DARPA-BAA-12-13@darpa.mil

PROPOSERS ARE CAUTIONED THAT EVALUATION RATINGS MAY BE LOWERED

AND/OR PROPOSALS REJECTED IF PROPOSAL PREPARATION (PROPOSAL FORMAT,

CONTENT, ETC.) AND/OR SUBMITTAL INSTRUCTIONS ARE NOT FOLLOWED.

THOSE INTENDING TO SUBMIT A PROPOSAL FOR AN ASSISTANCE INSTRUMENT

(GRANT OR COOPERATIVE AGREEMENT) ARE STRONGLY ENCOURAGED TO READ

THE INSTRUCTIONS PROVIDED AT SECTION IV(B)(4) REGARDING THE TIME

REQUIRED TO RECEIVE VALIDATION OF SUBMISSIONS MADE THROUGH

GRANTS.GOV. PROPOSALS THAT ARE VALIDATED AFTER THE PROPOSAL DUE

DATE/TIME WILL BE CONSIDERED LATE AND, AS SUCH, WILL NOT BE REVIEWED.

mailto:William.Chappell@darpa.mil mailto:name@darpa.mil

Part II: Full Text of Announcement

Sec. I: FUNDING OPPORTUNITY DESCRIPTION

The Defense Advanced Research Projects Agency often selects its research efforts through the Broad Agency Announcement (BAA) process. The BAA will appear first on the FedBizOpps website, http://www.fedbizopps.gov/, and Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA.

DARPA is soliciting innovative research and development (R&D) proposals in the area of Radio Frequency Field Programmable Gate Arrays (RF-FPGAs), a thrust within the DARPA Microsystems Technology Office’s Adaptive RF Technology (ART) program. The goal of RF- FPGA is to enable a common hardware architecture that facilitates reutilization of the same set of RF front-end components across disparate applications through programmability of the transceiver chain. RF-FPGAs will impact the areas of communications, electronic warfare, and signal intelligence by eliminating redundant and costly hardware development required for the adoption or recognition of a new wireless function or waveform. For the purposes of this program, ‘FPGA’ is used as a familiar term to represent analog circuitry with reprogrammable functions such as those found in a digital FPGA; it is not meant to imply that the RF-FPGA strictly utilizes typical gate-level digital FPGA hardware. However, DARPA envisions that the hardware resulting from this program will realize dynamically programmable analog and RF blocks similar in purpose to the digital FPGA slice. To prove this capability, this program will develop blocks of reconfigurable components and fully programmable transceivers capable of configuring for a variety of wireless applications while maintaining near optimal performance.

Additionally, it is expected that the hardware developed from this program will be capable of adapting to future wireless standards, thus positively impacting upgrade and procurement costs.

DARPA maintains that this goal can only be achieved by investigating the ability to adapt, switch or otherwise alter the RF front end with flexibility far beyond the current demonstrated capabilities of tunable systems and existing multi-band radios.

There are expected trade-offs between system or component adaptability, reconfiguration speed, the breadth of waveform coverage and the quality of service/data fidelity; optimizing this design space is a critical aspect to this effort. To meet these adaptability requirements, DARPA envisions that proposed architectures will comprise ‘fine-grained’ transistor-level reprogrammable blocks and/or ‘coarse-grained’ reprogrammable blocks containing blocks of tunable amplifiers, mixer stages, filters, matching networks, etc. It is anticipated that combinations of these types of FPGA-like elements will represent a significant increase in flexibility and adaptability compared to the current state of the art. Figure 1 conceptually shows the potential instantiations of ‘coarse’ and ‘fine’-grained adaptability compared to parallel arrays of fixed front-end chains.

Figure 1: Comparison of “coarse-grained” and “fine-grained” RF-FPGA architectures to current state-of-the-art

It is anticipated that banks of reconfigurable components (LNAs, mixers, power amplifiers, etc.)

may be investigated by smaller, focused efforts, while full reconfigurable transceiver capabilities may be demonstrated by larger teams. Teams of any size may also propose efforts related to computer-aided design (CAD) and FPGA-like programming tools for designing and configuring RF-FPGA hardware. In all cases, DARPA envisions that RF-FPGAs will positively impact the life cycle cost by providing DoD designers with a toolkit of reprogrammable functions that eliminate the need to re-design, manufacture and service multiple waveform or system-specific components across different platforms. An overarching goal, therefore, of this program is the ultimate reduction of costly and time consuming application-specific integrated circuit (ASIC) tape-outs by capturing the performance of multiple RF systems in a single RF-FPGA design cycle. Proposed research should investigate innovative approaches that enable revolutionary advances in integration of components, integrated circuit design, switching mechanisms, switchless designs, and/or algorithms. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice.

Background Digital FPGAs offer a cost-effective alternative to ASICs by providing a programmable and reconfigurable framework through which designers can develop and test multiple function implementations without the need for new hardware verification and fabrication re-spins. While some elements of performance are necessarily compromised, FPGAs are nevertheless becoming increasingly prevalent in DoD systems due to the increased level of adaptability and the decreased level of non-recurring engineering investment. Unlike digital design, however, many aspects of RF/analog circuit design require intuition and craft that are not easily abstracted to higher level design languages or expressed as re-useable blocks in standard libraries. Therefore, field-programmable circuits have had limited applicability to analog and mixed-signal designs.

Consequently, as wireless waveforms and standards advance to maintain spectrum dominance and enable new capabilities, entirely new communications, electronic warfare and signal intelligence hardware designs are often required, leading to lengthy and costly development cycles. This program looks to change this approach by enabling the ability to make systems built on programmable RF primitives that provide overlapping but reconfigurable functionality, comparable to slices in digital FPGAs. It is anticipated that such a system will be capable of operating in the severely crowded and rapidly changing modern commercial and military spectral environment at a reduced overall component count and with a reduced development cost compared to conventional multi-band radios.

The continued monolithic integration of RF components has led to exceptionally advanced systems in chip-scale form factors, e.g. multiple channel phased arrays implemented on a single chip1. Similarly, it has been demonstrated that mixed signal systems-on-a-chip (SoC) designs, with RF and digital processing integrated together on a single chip, can perform full down conversion and processing tasks2. However, it has not been primarily a focus of the research community to demonstrate that the integration capabilities can lead to components that are widely applicable for many disparate systems. It is anticipated that this effort will push the boundaries in both integration levels and the ability to access and repurpose RF components dynamically. A major challenge for this program is demonstrating that multiple waveforms can be processed with high information fidelity for multiple purposes, including adapting frequency, sensitivity, and linearity based on requirements which may not be known at the time of the initial design.

The RF-FPGA BAA represents a thrust area under a larger DARPA/MTO program entitled Adaptive RF Technology (ART). Other thrust areas in ART include 1) reconfigurable and high- Q filter arrays, 2) highly linear RF amplifiers for high dynamic range receivers, & 3) low-energy signal classification for understanding spectrum occupancy and content. While these thrusts have primarily focused on component development, this RF-FPGA program will investigate the impact of reconfiguring blocks of components or the entire RF system such that it is near optimal regardless of the waveform it is tasked to process.

System Example and Expected Benefits An example application for an RF-FPGA-enabled system is a wireless sensing platform for cargo tracking. (This simple example is purely illustrative and should not be interpreted as a

1 Atesal, Y.A.; Cetinoneri, B.; Ho, K.M.; Rebeiz, G.M.; , "A Two-Channel 8–20-GHz SiGe BiCMOS Receiver With Selectable IFs for Multibeam Phased-Array Digital Beamforming Applications," Microwave Theory and Techniques, IEEE Transactions on , vol.59, no.3, pp.716-726, March 2011.

2 Broadcom, “Low-Power 802.11n with Bluetooth 2.1 + EDR and FM (Tx and Rx),” BCM4329 datasheet, Nov.

2008.

predilection towards any specific application.) An example of such a sensor could use a combination of GSM, WiFi, GPS, and satcom to relay tracking information to a central station.

This systems’ spectral field of regard spans from 800 MHz to 2.4 GHz, and the specific connectivity mode depends on the availability of a given network, gracefully transitioning to whichever is within range and provides the lowest cost of connectivity. Today, each of the four on-board wireless systems would likely be handled by separate, dedicated RF chains, even though the system only utilizes one of these functionalities at one time. This side-by-side approach is a viable solution for providing the currently specified functionality; however, even in this relatively simple example, the RF-FPGA concept is expected to improve the procurement, upgradability, testing, and sustainability of such a system. These factors are often more important than the initial cost of the system, especially for components which have a limited number of deployments and are intended to survive in the field for many years of use.

• Procurement: by providing a variety of RF functions in a single platform, an RF-FPGA reduces procurement cycle times due to the commonality of the hardware. For this cargo tracking example, a single RF device could be procured for each desired function, as opposed to procuring a separate WiFi board, GSM board, Iridium board, and GPS unit.

• Upgradability: much like the digital FPGA, the RF-FPGA will severely reduce upgrade times for the introduction of new waveforms or features. Fast upgradability is a critical factor in maintaining spectrum dominance. As networks are enhanced, the wireless hardware needs to upgrade as well to avoid obsolescence in the field, enhancing longevity and relevance of a single procured device. In this example, the cargo tracking system could update for emerging cellular standards (e.g. 4G) or update for different satcom standards (Iridium, Orbcomm, Globalstar, etc.) after the hardware has been taped-out for fabrication.

• Testing: the commonality of the components will simplify the testing needed for each state of the device. Consequently, the associated testing cost will be significantly reduced as well. Globally certified hardware eliminates the need for functionality verification by individual developer teams (as would be necessary for entirely new RFICs).

• Sustainability: the government may have access to a repository of many of these devices as opposed to having to source a specific wireless device. Enforcing a common form factor and standards for interfacing with the RF chain will make for easier sustainment after fielding a unit.

Proposers to this BAA should use similar examples of systems about which they are intimately knowledgeable as the basis for their proposal. Teams should identify at least five target wireless platforms with disparate system requirements. At a minimum, two of the five chosen platforms should utilize waveforms or standards for which the specifications are available in open literature, e.g. 802.11, GSM, etc. These target systems can reside in the areas of radar, EW, communications, signal intelligence, etc. The goal of the RF-FPGA program is to develop a single reconfigurable hardware platform capable of providing the functionality of each target system with no degradation in performance.

Technical Areas This BAA comprises three technical areas. A proposal should address a single technical area only. Teams may propose to multiple technical areas; however, a separate proposal is required for each area. Multiple proposals from one team should be atomically structured so that they may be selected independently of one another. Proposers should clearly indicate the frequency bands targeted by their implementation. The dollar amounts and the estimated number of funded teams associated with each of the areas are meant to be rough guides as to the relative scope of the respective efforts. DARPA reserves the ability to reallocate funds between areas based on the evaluation results of received proposals.

Technical Area One: Component-Level Reconfigurability The goal of this technical area is to investigate the reconfigurability and programmability of individual RF components or banks of such components. Examples include reconfigurable RF and IF filters, low-noise amplifiers, mixers, matching networks, power amplifiers, etc. One or more RF front-end components may be demonstrated through this technical area. Modules produced through this technical area should be universal programmable elements capable of insertion into a wide variety of RF systems. Such reconfigurable modules should demonstrate near identical performance to components developed specifically for that target insertion system.

Teams proposing to this area should identify at least five individual RF systems as discussed above. Teams should then select one or more components common to each target system and develop a reconfigurable and programmable replacement that is capable of duplicating the required functionality with little to no reduction in critical performance values such as dynamic range, error-vector magnitude, range, power efficiency, etc.

A further goal of the project should be to standardize the size of the components. Ideally, this would lead to the development of modules that utilize a QFN package or similar commercial standard. Alternatively, the reconfigurable components could be distributed as reusable analog IP open for use by DoD system integrators. In either case, all of the reconfigurable component variations in the RF system should maintain the exact same form factor across application platforms and lead to the standardization to the interface to the rest of the system.

Approximately $2-5M total is available for this technical area; 4-6 awards are anticipated in Area One.

Technical Area Two: Full Transceiver Reconfigurability The goal of this technical area is to investigate the reconfigurability and programmability of full RF transceivers. Teams proposing to this area should identify at least five current individual RF systems. Teams should then develop a reconfigurable and programmable transceiver capable of duplicating the functionality of these five systems in a single platform with little to no reduction in critical performance values such as dynamic range, error-vector magnitude, range, power efficiency, etc. It is also anticipated that certain performance gains could also be realized by reconfigurable components. For example, on the transmit side of the transceiver, the error vector magnitude degradation in a communication signal is dependent on the peak to average ratio of the signal for a given amplifier performance. Therefore, the ability to gracefully transition from one class of power amplifier to another is highly desirable to maximize power efficiency for a given application.

By the conclusion of the proposed effort, the demonstrated hardware should also show the capability of reconfiguring for arbitrary waveform characteristics not necessarily represented by the five or more initially targeted systems. The system must be shown to be capable of adapting to an unknown RF standard which may be encountered in the future. Therefore, DARPA explicitly discourages the proposal of dedicated RF-chains for specific waveforms even if the capabilities of the five target systems could be demonstrated in this manner.

A further goal of the project should be to standardize the size of the components. Ideally, this would lead to the development of modules that utilize a QFN package or similar commercial standard. The entire final RF transceiver system should be envisioned as a series of packages that comprise a board that is no more than 45 cm2 in area.

Approximately $15-20M total is available for this technical area; 2-3 awards are anticipated in Area Two.

Technical Area Three: Computer-Aided Design and Programming for RF-FPGAs A critical element to the realization of the RF-FPGA is a computer-aided design platform specialized for the design and integration of programmable RF elements. Digital FPGAs require several unique tools for reprogramming and design, and it is anticipated that this requirement will extend to RF-FPGAs as well. DARPA expects that CAD tools for RF-FPGAs will be extensions of existing circuit design tools and be focused on the specific challenges related to reprogrammable RF elements, such as the optimization of RF performance parameters across different use scenarios. High-level description languages for programmable analog components allowing for abstracted design are specifically desired. The initial demonstration should show a unique RF-FPGA design flow using a tool-kit of reconfigurable RF components. The proposed CAD tools or design flow should then demonstrate the ability to synthesize optimized hardware from a high-level system performance description in an automated fashion based on reconfiguring common RF components from the tool-kit. Finally, the CAD tools should demonstrate the ability to reconfigure the hardware based on the input of expected spectral conditions. Although not required of this BAA, it is expected that this functionality would lead directly to an on-board cognitive engine responsible for reconfiguring the RF-FPGA in real time.

CAD and programming tools should be agnostic to the end function desired from the hardware and should support as many end use cases as possible.

Approximately $5-10M total is available for this technical area; multiple awards of varying size are anticipated in Area Three.

Assumptions In this program, you may assume that you have situational awareness of the spectral conditions, environmental pressures or mission requirements that provide the stimuli for reconfiguration.

The on-chip cognitive engine that would make automatic decisions based on this information is specifically left to other programs. Performers are expected to demonstrate that your hardware has the ability to reconfigure based on provided input of available situational awareness. You may assume that the digital control can be off board and that external, non-integrated components are providing the control signals.

You may also assume that a state of the art A/D (or D/A) is available as the follow-on component to the adaptable front-end module. Ideally, this is a commercial state of the art A/D (or D/A). An argument may be made that a unique research grade A/D (or D/A) is required, but this will limit the applicability of the RF-FPGA hardware to certain systems. Performers should identify the digital interface specifications, and approaches should be agnostic to the specific A/D attached to the RF-FPGA. In other words, if the RF-FPGA was ported to a different system with a different A/D, the RF-FPGA should still function as originally designed.

Program Structure The following program structure is a suggested progression of reconfigurability from factory-level to true real-time field reprogrammability. Periodic hardware demonstrations are required for Technical Areas 1 and 2 to ensure proper progress against the overall program goals. For Technical Area 3, the software should demonstrate support for designing components and systems at that level of reconfigurability. A suggested program schedule and associated evaluation criteria are outlined in Table 1. Teams are free to propose a schedule more specific to their effort; however, the progression of reconfigurability should be clearly shown and critical design reviews and/or hardware demonstrations should be scheduled at appropriate intervals.

Table 1: Program Outline Stage 1 – ~14 months Stage 2 – ~14 months Stage 3 –~ 14 months Goals Factory

Reprogrammability Pre-Theater Adaptability

Dynamic in-Theater Adaptation

80% system functionality compared to SOA for 5 target systems, shown with separately measured components

90% system functionality compared to SOA for 5 target systems, shown with integrated receiver

95% performance of systems with dynamic capabilities shown

Demonstration Targets

Area 1: Individual component performance of a static device.

Area 1: Demonstration of tunable performance over selected bands; 1 second adaptation speed.

Area 1: Microsecond order of magnitude tunable performance.

Area 2: System performance based on separately measured device performance;

static performance of all 5 target systems expected

Area 2: Demonstration of multiple user-identified transceiver systems synthesized from a common RF- FPGA platform; 1 second adaptation speed.

Area 2: A single integrated system which handles all identified target systems in addition to unknown waveforms of DARPA’s choosing;

microsecond order of magnitude adaptation speed.

Area 3: Demonstration of design flow with common component tool-kit

Area 3: Automation of transceiver design based on higher level descriptions

Area 3: Demonstration of rapid analysis and adjustment of the RF- FPGA based on provided in-field spectral conditions

1) Stage 1: Factory Reprogrammability

In this stage, the proposed architecture should enable factory reprogrammability of components or transceivers without the need for a new RF/analog design cycle and tape-out.

In other words, the proposed hardware should be programmable for at least five different RF system applications at the factory or fabrication facility. Signal routing can be fixed at the factory, e.g. through an interposer or other back-end-of-the-line metallization; however, the underlying RF active hardware should remain common to each system. Dynamic reconfigurability is not explicitly required.

Proposals addressing Technical Area 1 will need to show reconfigurable component functionality. Proposals should also quantify the impact of the component performance with respect to system-level specifications. Each of the common tool kit components, when individually measured, should project to 80% of the system performance functionality of a specifically built component. For example, the noise figure metric for an LNA would have to be less than 20% worse than the noise figure of an LNA specifically designed for the target RF system. In other words, a noise figure of 3 dB for the target system would translate into a NF requirement of 3.8 dB in the RF-FPGA component (percentages should be calculated on linear values). Proposals should list target performance values from existing systems along with the expected performance of the RF-FPGA component.

Proposals addressing Technical Area 2 will need to show transceiver capability. The demonstration hardware should combine the capabilities of at least five existing RF systems with less than 20% degradation in performance for critical metrics as discussed above.

Proposals should list target performance values from existing systems along with the expected performance of the designed transceiver.

Proposals addressing Technical Area 3 will need to demonstrate a RF-FPGA design flow utilizing a common component tool-kit. The developed software should demonstrate simulation capability for chains of reconfigurable components and identify critical system performance trade-offs.

2) Stage 2: Pre-theater Adaptation

In this stage, the proposed architecture should exhibit pre-theater adaptation. In other words, tuning and reconfiguration can be set after fabrication and before deployment into the field.

This level of reprogrammability will allow for adaptation to network trends and intelligence in the network, e.g. the need for a filter null in a particular frequency location based on operational history of other devices in that particular region of a network. Therefore, dynamic switching is required, but not at real-time and at much slower time-scales than in-theater adaptation. This level of reconfigurability will also make the components or transceiver robust to manufacturing and assembly variations.

Proposals addressing Technical Area 1 should show dynamic reconfigurable component functionality. Proposals should also quantify the impact of the component performance with respect to system-level specifications. Each of the common tool kit components, when individually measured, should project to 90% of the system performance functionality of a specifically built component. Proposals should list target performance values from existing state of the art systems along with the expected performance of the RF-FPGA component.

Proposals addressing Technical Area 2 should show dynamic reconfigurable transceiver capability. The demonstration hardware should combine the capabilities of at least five existing RF systems with less than 10% degradation in performance for critical metrics as discussed above. Proposals should list target performance values from existing systems along with the expected performance of the designed transceiver

Proposals addressing Technical Area 3 should demonstrate automation of transceiver design based on higher level descriptions of hardware primitives. The developed tools should demonstrate automated hardware design based on the input of waveform specifications and expected spectral conditions in the field.

3) Stage 3: In-Theater Adaptation

The level of adaptation expected in this stage is a dynamic reaction to the current spectrum environment. As conditions in the field change, the RF device will need to adapt as well.

This is a level of functionality beyond even current digital FPGAs in some aspects; however, this is highly desirable in the RF domain as the spectrum rapidly evolves. A performer may assume knowledge of the changing events around the system; however, it must be clear that the level of adaptation is sufficiently fast to make relevant changes with low enough loss that the advantages afforded by adaptability are not lost. The components and transceiver should withstand a large number of adaptations, and therefore reliability of the adaptable mechanism is of primary importance.

An example scenario is the ability of an RF system to alter the architecture or component capabilities in order to operate in the presence of a large interferer. An example of this would be the operation as a mobile operator becomes nearer to a TV station tower. If the RF receiver is to operate in the presence of the interferer, both the filter and the topology of the receiver may change. For adjacent channel interference, the receiver may need to switch to a higher linearity. For out of band interference, an adaptable filter may remove the unwanted interference. To cover all cases, a combination of the two would be necessary. For example, the use of a passive mixer may be desired with an amplifier that has high TOI, and a filter which is altered to specifically null the TV station threat. To demonstrate resiliency in the presence of larger interferers, the RF-FPGA performance should not degrade in the presence of narrowband and wideband jamming signals from 10% to 0.1% away from the carrier frequency.

Proposals addressing Technical Area 1 should show full real-time dynamic component functionality. Additionally, the components must show the ability to reconfigure for waveforms or functions that are unknown to the designer a priori. Proposals should also be required to quantify the impact of the component performance with respect to system-level specifications. Each of the common tool kit components, when individually measured, should project to 95% of the system performance functionality of a specifically built component.

Proposals should list target performance values from existing systems along with the expected performance of the designed RF-FPGA component.

Proposals addressing Technical Area 2 should show real-time dynamic transceiver capability.

The demonstration hardware should combine the capabilities of at least five existing RF systems with no degradation in performance for critical metrics as discussed above.

Furthermore, the transceiver must show the ability to reconfigure for waveforms or functions that are unknown to the designer a priori. Each proposal should list target performance values from existing systems along with the expected performance of the transceiver.

Proposals addressing Technical Area 3 will need to demonstrate rapid analysis and adjustment of the RF-FPGA based on in-field spectral conditions. Software resulting from this effort could lead to the implementation of on-board cognitive engine responsible for real-time reconfiguration of the RF-FPGA hardware.

Sec II. AWARD INFORMATION

Multiple awards are anticipated. The amount of resources made available under this BAA will depend on the quality of the proposals received and the availability of funds.

The Government reserves the right to select for negotiation all, some, one, or none of the proposals received in response to this solicitation, and to make awards without discussions with proposers. The Government also reserves the right to conduct discussions if it is later determined to be necessary. If warranted, portions of resulting awards may be segregated into pre-priced options. Additionally, DARPA reserves the right to accept proposals in their entirety or to select only portions of proposals for award. In the event that DARPA desires to award only portions of a proposal, negotiations may be opened with that proposer. The Government reserves the right to fund proposals in phases with options for continued work at the end of one or more of the phases.

Awards under this BAA will be made to proposers on the basis of the evaluation criteria listed below (see section labeled “Application Review Information”, Sec. V.), and program balance to provide overall value to the Government. Proposals identified for negotiation may result in a procurement contract, grant, cooperative agreement, or other transaction depending upon the nature of the work proposed, the required degree of interaction between parties, and other factors. The Government reserves the right to request any additional, necessary documentation once it makes the award instrument determination. Such additional information may include but is not limited to Representations and Certifications. The Government reserves the right to remove proposers from award consideration should the parties fail to reach agreement on award terms, conditions and cost/price within a reasonable time or the proposer fails to timely provide requested additional information.

As of the date of publication of this BAA, DARPA expects that program goals for this BAA may be met by proposers intending to perform 'fundamental research,' i.e., basic or applied research performed on campus in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization the results of which ordinarily are restricted for proprietary or national security reasons. Notwithstanding this statement of expectation, DARPA is not prohibited from considering and selecting research proposals that, while perhaps not qualifying as 'fundamental research' under the foregoing definition, still meet the BAA criteria for submissions. If proposals are selected for award that offer other than a fundamental research solution, then DARPA will either work with the proposer to modify the proposed statement of work to bring the research back into line with fundamental research or else the proposer will agree to restrictions in order to receive an award. See Section VI.B.4 for further information on fundamental, non-fundamental and restricted research. In all cases, the DARPA contracting officer shall have sole discretion to select award instrument type and to negotiate all instrument provisions with selectees.

Sec. III: ELIGIBILITY INFORMATION

A. Eligible Applicants

All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA. Historically Black Colleges and Universities (HBCUs), Small Businesses, Small Disadvantaged Businesses and Minority Institutions (MIs) are encouraged to submit proposals and join others in submitting proposals; however, no portion of this announcement will be set aside for these organizations’ participation due to the impracticality of reserving discrete or severable areas of this research for exclusive competition among these entities.

Federally Funded Research and Development Centers (FFRDCs) and Government entities (Government/National laboratories, military educational institutions, etc.) are subject to applicable direct competition limitations and cannot propose to this BAA in any capacity unless they address the following conditions. FFRDCs must clearly demonstrate that the proposed work is not otherwise available from the private sector AND must also provide a letter on letterhead from their sponsoring organization citing the specific authority establishing their eligibility to propose to government solicitations and compete with industry, and compliance with the associated FFRDC sponsor agreement and terms and conditions. This information is required for FFRDCs proposing to be prime or subcontractors. Government entities must clearly demonstrate that the work is not otherwise available from the private sector and provide written documentation citing the specific statutory authority (as well as, where relevant, contractual authority) establishing their ability to propose to Government solicitations. At the present time, DARPA does not consider 15 U.S.C. 3710a to be sufficient legal authority to show eligibility.

While 10 U.S.C. 2539b may be the appropriate statutory starting point for some entities, specific supporting regulatory guidance, together with evidence of agency approval, will still be required to fully establish eligibility. DARPA will consider eligibility submissions on a case-by-case basis; however, the burden to prove eligibility for all team members rests solely with the Proposer.

B. Procurement Integrity, Standards of Conduct, Ethical Considerations, and Organizational Conflicts of Interest

Current federal employees are prohibited from participating in particular matters involving conflicting financial, employment, and representational interests (18 USC 203, 205, and 208).

The DARPA Program Manager for this BAA is (Program Manager). Once the proposals have been received, and prior to the start of proposal evaluations, the Government will assess potential conflicts of interest and will promptly notify the Proposer if any appear to exist. (Please note, the Government assessment does NOT affect, offset, or mitigate the Proposer’s own duty to give full notice and planned mitigation for all potential organizational conflicts, as discussed below.)

Without prior approval or a waiver from the DARPA Director, in accordance with FAR 9.503, a Contractor cannot simultaneously provide scientific, engineering, technical assistance (SETA) or similar support and also be a technical performer. Therefore, all Proposers as well as proposed subcontractors and consultants must affirm whether they (their organizations and individual team members) are providing SETA or similar support to any DARPA technical office(s) through an active contract or subcontract. All affirmations must state which office(s) the Proposer, subcontractor, consultant, or individual supports and identify the prime contract number(s).

Affirmations shall be furnished at the time of proposal submission. All facts relevant to the existence or potential existence of organizational conflicts of interest (FAR 9.5) must be disclosed. The disclosure must include a description of the action the Proposer has taken or proposes to take to avoid, neutralize, or mitigate such conflict. If in the sole opinion of the Government after full consideration of the circumstances, a proposal fails to fully disclose potential conflicts of interest and/or any identified conflict situation cannot be effectively mitigated, the proposal will be rejected without technical evaluation and withdrawn from further consideration for award.

If a prospective Proposer believes that any conflict of interest exists or may exist (whether organizational or otherwise) or has questions on what constitutes a conflict of interest, the Proposer should promptly raise the issue with DARPA by sending his/her contact information and a summary of the potential conflict to the BAA mailbox before time and effort are expended in preparing a proposal and mitigation plan.

C. Cost Sharing/Matching

Cost sharing is not required for this particular program; however, cost sharing will be carefully considered where there is an applicable statutory condition relating to the selected funding instrument (e.g., for any Other Transactions under the authority of 10 U.S.C. § 2371). Cost sharing is encouraged where there is a reasonable probability of a potential commercial application related to the proposed research and development effort.

Sec. IV: APPLICATION AND SUBMISSION INFORMATION

A. Address to Request Application Package

This solicitation contains all information required to submit a proposal. No additional forms, kits, or other materials are needed. This notice constitutes the total BAA. No additional information is available, nor will a formal Request for Proposal (RFP) or additional solicitation regarding this announcement be issued. Requests for same will be disregarded.

B. Content and Form of Application Submission

1. Security and Proprietary Issues

NOTE: If proposals are classified, the proposals must indicate the classification level of not only the proposal itself, but also the anticipated award document classification level.

The Government anticipates proposals submitted under this BAA will be unclassified. However, if a proposal is submitted as “Classified National Security Information” as defined by Executive Order 13526, then the information must be marked and protected as though classified at the appropriate classification level and then submitted to DARPA for a final classification determination.

Security classification guidance via a DD Form 254, “DoD Contract Security Classification Specification,” will not be provided at this time, since DARPA is soliciting ideas only. After reviewing the incoming proposals, if a determination is made that the award instrument may result in access to classified information, a DD Form 254 will be issued and attached as part of the award.

Proposers choosing to submit a classified proposal from other classified sources must first receive permission from the respective Original Classification Authority in order to use their information in replying to this BAA. Applicable classification guide(s) should also be submitted to ensure the proposal is protected at the appropriate classification level.

Classified submissions shall be appropriately and conspicuously marked with the proposed classification level and declassification date. Submissions requiring DARPA to make a final classification determination shall be marked as follows:

CLASSIFICATION DETERMINATION PENDING. Protect as though classified (insert the recommended classification level: (e.g., Top Secret, Secret or Confidential)

Classified submissions shall be in accordance with the following guidance:

Confidential and Secret Collateral Information: Use classification and marking guidance provided by previously issued security classification guides, the Information Security Regulation (DoD 5200.1-R), and the National Industrial Security Program Operating Manual (DoD 5220.22-M) when marking and transmitting information previously classified by another Original Classification Authority. Classified information at the Confidential and Secret level may be submitted via ONE of the two following methods:

1. Hand-carried by an appropriately cleared and authorized courier to the DARPA CDR. Prior to traveling, the courier shall contact the DARPA CDR at 703-526-4052 to coordinate arrival and delivery.

OR

2. Mailed via appropriate U.S. Postal Service methods (e.g., (USPS)

Registered Mail or USPS Express Mail). All classified information will be enclosed in opaque inner and outer covers and double wrapped. The inner envelope shall be sealed and plainly marked with the assigned classification and addresses of both sender and addressee.

The inner envelope shall be addressed to:

Defense Advanced Research Projects Agency ATTN: Microsystems Technology Office Reference: DARPA-BAA-12-13 3701 North Fairfax Drive Arlington, VA 22203-1714

The outer envelope shall be sealed with no identification as to the classification of its contents and addressed to:

Defense Advanced Research Projects Agency Security & Intelligence Directorate, Attn: CDR 3701 North Fairfax Drive Arlington, VA 22203-1714

All Top Secret materials: Top Secret information should be hand carried by an appropriately cleared and authorized courier to the DARPA CDR. Prior to traveling, the courier shall contact the DARPA CDR at 703-526-4052 to coordinate arrival and delivery.

Special Access Program (SAP) Information: SAP information must be transmitted via approved methods. Prior to transmitting SAP information, contact the DARPA SAPCO at 703- 526-4052 for instructions.

Sensitive Compartmented Information (SCI): SCI must be transmitted via approved methods. Prior to transmitting SCI, contact the DARPA Special Security Office (SSO) at 703- 526-4052 for instructions.

Proprietary Data: All proposals containing proprietary data should have the cover page and each page containing proprietary data clearly marked as containing proprietary data. It is the Proposer’s responsibility to clearly define to the Government what is considered proprietary data.

Proposers must have existing and in-place prior to execution of an award, approved capabilities (personnel and facilities) to perform research and development at the classification level they propose. It is the policy of DARPA to treat all proposals as competitive information, and to disclose their contents only for the purpose of evaluation. Proposals will not be returned. The original of each proposal received will be retained at DARPA and all other non-required copies destroyed. A certification of destruction may be requested, provided the formal request is received at this office within 5 days after unsuccessful notification.

2. Abstract Submission Information

Proposers are strongly encouraged to submit an abstract in advance of a full proposal. This procedure is intended to minimize unnecessary effort in proposal preparation and review. The time and date for submission of abstracts is specified in Section IV.B.6 (Submission Dates and Times) below. DARPA will acknowledge receipt of the submission and assign a control number that should be used in all further correspondence regarding the abstract.

Upon review, DARPA will provide written feedback on the likelihood of a full proposal being selected and the time and date for submission of a full proposal, which may differ from the originally published date below.

3. Abstract Format

Abstracts are encouraged in advance of full proposals in order to provide potential proposers with a rapid response to minimize unnecessary effort. Abstracts should follow the format outlined below; maximum page lengths for each section are shown in braces { }. The cover sheet should be clearly marked “ABSTRACT” and the total length should not exceed 15 pages, excluding the Administrative Cover Sheet. All pages shall be printed on 8-1/2 by 11 inch paper with type not smaller than 12 point. Smaller font may be used for figures, tables and charts. The page limitation for abstracts includes all figures, tables, and charts. No formal transmittal letter is required. All abstracts must be written in English.

Section I. Administrative Cover Sheet

Include the following information:

(1) BAA number

(2) Technical areas

(3) Lead Organization submitting proposal

(4) Type of business, selected among the following categories: “LARGE BUSINESS”, “SMALL DISADVANTAGED BUSINESS”, “OTHER SMALL BUSINESS”, “HBCU”, “MI”, “OTHER EDUCATIONAL”, OR “OTHER NONPROFIT”

(5) Contractor’s reference number (if any)

(6) Other team members (if applicable) and type of business for each

(7) Proposal title

(8) Technical point of contact to include: salutation, last name, first name, street address, city, state, zip code, telephone, fax (if available), electronic mail

(9) Administrative point of contact to include: salutation, last name, first name, street address, city, state, zip code, telephone, fax (if available), electronic mail

(10) Total funds requested from DARPA, and the amount of cost share (if any) AND

(11) Date proposal was submitted.

Section II. Abstract

A. {3} Summary of the innovative claims for the proposed research. This section should succinctly describe the uniqueness and benefits of the proposed approach relative to the current state-of-art alternate approaches. This section should demonstrate that the proposer has a clear understanding of the state-of-the-art and should provide sufficient technical details so as to permit complete evaluation of the feasibility of the idea.

B. {2} Metrics and target system description. Proposers should describe the target systems used to benchmark the functionality that will be demonstrated in the RF-FPGA. The metrics associated with each of the target systems should be demonstrable and quantitative measures of performance and should be summarized in table format.

C. {3} Summary of the technical rationale, technical approach, and constructive plan for accomplishment of technical goals in support of innovative claims and deliverable production. (A more detailed plan will be solicited for the full proposal.) Proposals should clearly explain the technical approach(es) that will be employed to meet or exceed each program and performer-defined metric and provide ample justification as to why the approach(es) is/are feasible.

D. {2} Summary of the deliverables associated with the proposed research and the plans and capability to accomplish technology transition and commercialization. Proposers should quantify the impact that the proposed RF-FPGA concept will have on procurement, upgradability, testing and sustainability of DoD systems.

E. {1} General discussion of other research in this area. Succinct comparison with other ongoing research shall be provided indicating advantages and disadvantages of the proposed…