ipEngine 1 - Specifications and Requirements.pdf

ipEngine‐1 Specifications & Requirements

66 MIPS power PC CPU

16 MB DRAM

4 MB FLASH

10Base‐T Ethernet On‐Board 16 Watt Power Supply 16,000 Gate FPGA 132 Pin Virtual I/O Interface USB Host/Slave Controller LCD/Video Controller Dual RS‐232 Built‐In Real‐Time Network OS and Web Server Integrated Development Tools

CPU

Motorola MPC823 @ 0‐50 MHz On‐Chip Peripherals:

Ethernet USB Host/Slave 2 Serial Channels LCD/Video Controller I2C Serial Bus

Memory 4Mx32 60ns EDO DRAM 2Mx16 90ns BootBlock FLASH

FPGA Based Virtual I/O Interface Altera EPF6016 16,000 Gate FPGA 64K x 16 Sync SRAM 1 – 50 MHz Programmable Clock Generator 88 Pins “Virtual I/O’

Power Supply Input: 7‐18V unregulated DC or regulated 5VDC Output: 5.0V @ 2 amps (with 7‐18V input) 3.3V @ 2 amps Efficiency: 95%

Power Consumption 25mW – 2 Watts depending on application

Integrated Real‐Time OS POSIX‐based Kernel POSIX Threads Full‐Compliment of Network Protocols:

TCP/IP, UDP, ICMP, ARP, IGMP, DNS

FTP, TFTP, HTTP, DHCP

TELNET

Berkeley Sockets Command Line Shell Embedded Web Server Flash File System URL/Web based File System Remote “Over‐the‐Network” Debugging Boot Loader for support of third‐party RTOS

Integrated Development Tools GNU based C/C++Cross‐Development No‐Cost FPGA Tools available from Altera Web Site