Project Grant 2520332

COLLABORATIVE RESEARCH: ASCENT: HETEROGENEOUSLY INTEGRATED ELECTRONIC PHOTONIC AI ACCELERATORS (HIEPAA) -NONTECHNICAL DESCRIPTION THE RAPID ADVANCEMENT OF DEEP NEURAL NETWORKS (DNNS) AND LARGE LANGUAGE MODELS (LLMS) IS TRANSFORMING MANY FACETS OF MODERN SOCIETY. THESE AI MODELS ARE TRAINED AND DEPLOYED IN DATA CENTERS POWERED BY SPECIALIZED HARDWARE SUCH AS GRAPHICS PROCESSING UNITS (GPUS), RESULTING IN SIGNIFICANT ENERGY DEMANDS AND RAISING CRITICAL CONCERNS AROUND SUSTAINABILITY AND ENERGY SECURITY. THIS PROJECT AIMS TO EXPLORE THE USE OF LIGHT FOR PERFORMING NEURAL NETWORK COMPUTATIONS, ENABLING THE DEVELOPMENT OF ENERGY-EFFICIENT AI HARDWARE. SPECIFICALLY, THE PROJECT WILL LEVERAGE THE INTEGRATION OF THIN-FILM LITHIUM NIOBATE (TFLN) ? A HIGH-PERFORMANCE ELECTRO-OPTIC MATERIAL ? WITH SILICON PHOTONIC CHIP PLATFORMS TO FABRICATE ANALOG OPTICAL MODULATORS THAT OFFER SIGNIFICANTLY LOWER LOSS AND HIGHER SPEED COMPARED TO TRADITIONAL SILICON-BASED DEVICES. IN ADDITION, THE PROJECT WILL DESIGN NEW ARCHITECTURES AND CIRCUIT TECHNIQUES TO ACHIEVE HIGH-RESOLUTION AI COMPUTATION USING LOW-PRECISION BUILDING BLOCKS, OPTIMIZING BOTH EFFICIENCY AND ACCURACY. THE EDUCATIONAL COMPONENT OF THIS PROJECT WILL TRAIN STUDENTS IN BOTH PHOTONIC AND ADVANCED ELECTRONIC CHIP DESIGN, EQUIPPING THEM WITH THE SKILLS ESSENTIAL FOR NEXT-GENERATION AI HARDWARE DEVELOPMENT. OUTREACH TO HIGH-SCHOOL STUDENTS USING AI-BASED PROJECTS WILL HELP BUILD A PIPELINE OF STUDENTS TO PURSUE ENGINEERING DEGREES FOCUSING ON SEMICONDUCTORS AND AI. THE INDUSTRY SPONSOR WILL BE ACTIVELY ENGAGED AS A STRATEGIC PARTNER TO HELP TRANSITION THE TECHNOLOGY FROM RESEARCH PROTOTYPES TO REAL-WORLD DEPLOYMENT. TECHNICAL DESCRIPTION THE HETEROGENEOUSLY-INTEGRATED ELECTRONIC-PHOTONIC AI ACCELERATOR (HIEPAA) PROJECT FEATURES CROSS-LAYER INNOVATIONS FROM DEVICE DESIGN TO INTEGRATED CIRCUITS, TO WAFER-SCALE ARCHITECTURE TO ACHIEVE SIGNIFICANT IMPROVEMENTS IN THROUGHPUT AND ENERGY EFFICIENCY OF AI ACCELERATORS. BY COMBINING CO-PACKAGED ELECTRONIC-PHOTONIC ICS (EPICS) WITH BONDED TFLN MODULATORS PROMISING ABOVE 50 GHZ BANDWIDTH AND EXTREMELY LOW LOSS, THIS ARCHITECTURE WILL ENABLE SPACE-TIME MULTIPLEXED COMPUTATIONS, DELIVERING OVER 2 TERA OPERATIONS PER SECOND (TOPS) PER TILE WITH 2 TOPS/W ENERGY-EFFICIENCY AND SCALING TO 1 EXAOPS PERFORMANCE AT THE WAFER SCALE WITH 200 TOPS/W ENERGY-EFFICIENCY. ARCHITECTURAL INNOVATIONS WILL SOLVE THE LONG-STANDING CHALLENGE ASSOCIATED WITH THE PRECISION AND ENERGY CONSUMPTION TRADEOFF OF DATA CONVERTERS AND DEVICES USED IN THE ACCELERATOR TILE BY INVESTIGATING RESIDUE NUMBER SYSTEM (RNS)-BASED PHOTONIC VMM ARCHITECTURE. THE EPIC PHOTONIC CORE WILL SUPPORT COHERENT VECTOR-MATRIX MULTIPLICATION (VMM) AT UP TO 60 GS/S SYMBOL RATES. THE SPACE-TIME MULTIPLEXED ARCHITECTURE WILL ENABLE FLEXIBLE VMM OPERATIONS WITH VECTOR LENGTHS RANGING OVER 1000S TO PERFORM INFERENCE ON TRANSFORMER-BASED LLM MODELS. FABRICATED PICS AND EICS WILL BE INDEPENDENTLY VERIFIED, PACKAGED, AND INTEGRATED INTO A SYSTEM, WITH A PACKAGED PRINTED CIRCUIT BOARD (PCB) PROTOTYPE WITH A FIELD-PROGRAMMABLE GATE ARRAY (FPGA)-BASED DIGITAL BACKEND TO VALIDATE THE HIEPAA TILE'S PERFORMANCE ON THE STATE-OF-THE-ART LLM MODELS, WHICH WILL GUIDE WAFER-SCALE ARCHITECTURAL PERFORMANCE BENCHMARKING. A COMPREHENSIVE EDUCATION AND WORKFORCE DEVELOPMENT PLAN WILL FOCUS ON BUILDING EXPERTISE IN ELECTRO-OPTIC AI ACCELERATOR ARCHITECTURE, PHOTONIC AND ELECTRONIC CHIP DESIGN, AND AI AND MACHINE LEARNING. A KEY EMPHASIS IS TO FAST-TRACK THE TRAINING OF STUDENTS ON NEWER FINFET CMOS NODES THROUGH A COMPLETE REVAMP OF ANALOG IC DESIGN COURSES AND DEVELOPING STRUCTURED TRAINING MATERIAL WITH A FOCUS ON PHOTONICS IC DESIGN. NEW UNDERGRADUATE RESEARCH OPPORTUNITIES WILL BE INTRODUCED TO SUSTAIN THE TRADITION OF INVOLVING UNDERGRADUATES IN THE PIS' LABS THROUGH SUMMER SCHOLAR PROGRAMS AND NSF-SPONSORED REU INITIATIVES. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE NOT PLANNED FOR THIS AWARD.