This $292,568 Project Grant award from the National Science Foundation's (NSF) Computer and Information Science and Engineering (CISE) program (CFDA 47.070) will fund research at Cornell University to develop techniques for efficient debugging and profiling of hardware accelerator designs. The project aims to reduce the time and cost of developing efficient specialized hardware to support computationally intensive applications. Key focus areas include:
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Developing methods for collecting data on resource consumption, critical timing paths, and cycle-level timing to generate visualizations of accelerator efficiency metrics.
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Creating a new approach to combine the observability of software simulation with the speed of FPGA emulation, allowing detailed inspection of accelerator execution states.
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Designing mechanisms to understand and expose concurrency bugs in accelerator designs by systematically manipulating execution schedules.
This award will also support a new cross-institutional community for industry and academic collaboration on open-source projects related to accelerator design languages and associated tools. The performance period for this grant is from October 1, 2024 to September 30, 2027.
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