Not listed
FUSE2 TOPIC 3: HIGH-PERFORMANCE & ENERGY-EFFICIENT IN-MEMORY COMPUTING DEVICES WITH CO-DESIGNED 2D FERROELECTRIC MATERIALS AND STACKS -NONTECHNICAL DESCRIPTION PROCESSING AND MEMORY TAKE PLACE IN DIFFERENT PARTS OF TRADITIONAL COMPUTERS. DATA IS TRANSFERRED FROM LONG TERM STORAGE INTO MEMORY, AND THEN PASSES BACK AND FORTH BETWEEN MEMORY AND THE CPU. THESE PROCESSES INEVITABLY LIMIT THE INFORMATION PROCESSING SPEED, AND INCREASINGLY CONSUME GREATER AMOUNTS OF ENERGY. GIVEN THAT DATA CENTERS CONSUME MORE THAN 1% OF ELECTRICAL POWER WORLDWIDE, THERE IS A PRESSING NEED FOR FAST, ENERGY EFFICIENT COMPUTING. SUCH A CHALLENGE TRIGGERS THE WIDESPREAD INTEREST IN DEVELOPING LOGIC-IN-MEMORY HARDWARE, WHERE THE LATENT TIME IN DATA PROCESSING CAN BE EFFECTIVELY MINIMIZED. FOR THIS QUEST, THE TEAM SEEKS TO REALIZE AN ENERGY EFFICIENT LOGIC-MEMORY BIFUNCTIONAL DEVICE. FERROELECTRIC TUNNEL JUNCTIONS (FTJS) ARE A CRITICAL CLASS OF NON-VOLATILE MEMORY DEVICES HOLDING UNIQUE PROMISE BECAUSE THEY CAN BE SEAMLESSLY INTEGRATED WITH THE CONTEMPORARY SILICON CHIP PLATFORM. THE OVERARCHING GOAL OF THIS PROJECT IS TO DEVELOP HIGH-PERFORMANCE, ENERGY-EFFICIENT FTJS FOR IN-MEMORY COMPUTING, BASED ON THE CO-DESIGNED TWO-DIMENSIONAL (2D) VAN DER WAALS FERROELECTRIC MATERIALS, INTERFACES, AND MULTILAYER STACKS. TO REALIZE THIS VISION, THREE MAIN FIGURES OF MERIT FOR THE FTJS NEED TO BE REALIZED IN THE SAME DEVICE: LOW SWITCHING VOLTAGES, HIGH ON/OFF RATIOS, AND HIGH ON-STATE CURRENT DENSITIES. THE TEAM APPLIES FIRST-PRINCIPLES CALCULATION, QUANTUM TRANSPORT SIMULATION, HIGH-QUALITY BULK CRYSTALS AND THIN FILMS SYNTHESIS AND CHARACTERIZATION, AND FTJ NANODEVICES FABRICATION AND CHARACTERIZATION, TO CO-DESIGN 2D FERROELECTRICS WITH LOW COERCIVE FIELD AND OPTIMIZED METAL/2D FERROELECTRICS/GRAPHENE FTJ STACKS WITH HIGH ON/OFF RATIO AND HIGH ON-STATE CURRENT DENSITY. THE TEAM EMPLOYS A CO-DESIGN PHILOSOPHY, WITH A STRATEGIC PLAN TO DEVELOP THE MATERIALS AND DEVICES THROUGH SCALABLE SYNTHESIS AND MANUFACTURING TECHNIQUES. THIS BRINGS THE RESEARCH OUTCOMES OF THIS PROJECT CLOSER TO INDUSTRY-COMPATIBLE REALIZATIONS. THE TEAM CONDUCTS WORKFORCE TRAINING THROUGH WORKSHOPS (E.G., ?QUANTUM + CHIPS? SUMMER PROGRAM), AND TRAINS STUDENTS IN DEVICE PHYSICS AND FABRICATION EXPERTISE THAT ARE CRITICALLY NEEDED FOR A GREATER MICROELECTRONICS WORKFORCE IN THE U.S. THE TEAM?S EDUCATION PLANS ALSO INCLUDE COURSE MATERIAL DEVELOPMENT OUT OF THIS UNIQUE MATERIAL/DEVICE CO-DESIGN RESEARCH AND THE CONTINUED OUTREACH TO STUDENTS OF UNDERREPRESENTED GROUPS BOTH IN CO-PIS? THREE REGIONS AND NATIONALLY. TECHNICAL DESCRIPTION FERROELECTRIC TUNNEL JUNCTIONS (FTJS) ARE CRITICAL NON-VOLATILE MEMORY DEVICES THAT CAN BE SEAMLESSLY INTEGRATED WITH THE SILICON CHIP PLATFORM. THIS INTEGRATION OF FTJS INTO SILICON MICROELECTRONICS CAN FACILITATE THE PHYSICAL PROXIMITY BETWEEN MEMORY AND LOGIC UNITS, THEREBY REDUCING THE CROSS-HARDWARE LATENT TIME AND ENABLING HIGH-SPEED DATA PROCESSING. IF AN FTJ MEMORY CAN ALSO FUNCTION AS A LOGIC DEVICE SUCH AS A TUNNELING FIELD EFFECT TRANSISTOR, IT WOULD THEN BE MEMORY-LOGIC BIFUNCTIONAL. SUCH A TECHNOLOGICAL BREAKTHROUGH WOULD BE MONUMENTAL FOR IN-MEMORY COMPUTING. TO ACHIEVE THIS GOAL, COMPELLING ADVANCES IN FTJS ARE NEEDED. SPECIFICALLY, THREE MAIN FIGURES OF MERIT IN PERFORMANCE AND ENERGY COST SHOULD BE SATISFIED: LOW SWITCHING VOLTAGES (E.G., 10,000,000,000), AND HIGH ON-STATE CURRENT DENSITIES (E.G., > 100,000 AMPERE PER CENTIMETER SQUARE). TO ACHIEVE THESE METRICS, THE TEAM PLANS TO CO-DESIGN 2D VDW FERROELECTRIC MATERIALS, INTERFACES, AND MULTILAYER STACKS, POTENTIALLY LEADING TO THREE ASPECTS OF KNOWLEDGE ADVANCES. FIRST, THE TEAM PLANS TO DEVELOP A NEW SYNTHESIS APPROACH FOR FERROELECTRIC IN2SE3 WITH ?NEGLIGIBLE DEFECTS,? AND USE THESE CRYSTALS TO EXPLORE THE INTRINSIC PROPERTIES (E.G., COERCIVITY) OF 2D FERROELECTRIC CRYSTALS AND THE INTRINSIC ELECTRON TUNNELING BEHAVIOR IN 2D FTJS. SECOND, THIS PROJECT AIMS TO ELUCIDATE THE FUNDAMENTAL RELATIONSHIP BETWEEN 2D FTJS? ON/OFF RATIO AND BASIC MATERIAL PARAMETERS INCLUDING BANDGAPS OF 2D FERROELECTRICS, GRAPHENE LAYER NUMBERS AND DOPING LEVELS, AND METAL WORK FUNCTIONS. THIRD, THIS PROJECT CAN EXPERIMENTALLY MAP OUT THE BAND ALIGNMENT INFORMATION BETWEEN CONVENTIONAL METALS AND 2D FERROELECTRICS, REVEALING THE RELATIONSHIP BETWEEN THE METAL/FERROELECTRIC BAND ALIGNMENT AND THE RESULTING ON-STATE CURRENT DENSITY. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.
$0 11/8/24 Not listed
FUSE2 TOPIC 3: HIGH-PERFORMANCE & ENERGY-EFFICIENT IN-MEMORY COMPUTING DEVICES WITH CO-DESIGNED 2D FERROELECTRIC MATERIALS AND STACKS -NONTECHNICAL DESCRIPTION PROCESSING AND MEMORY TAKE PLACE IN DIFFERENT PARTS OF TRADITIONAL COMPUTERS. DATA IS TRANSFERRED FROM LONG TERM STORAGE INTO MEMORY, AND THEN PASSES BACK AND FORTH BETWEEN MEMORY AND THE CPU. THESE PROCESSES INEVITABLY LIMIT THE INFORMATION PROCESSING SPEED, AND INCREASINGLY CONSUME GREATER AMOUNTS OF ENERGY. GIVEN THAT DATA CENTERS CONSUME MORE THAN 1% OF ELECTRICAL POWER WORLDWIDE, THERE IS A PRESSING NEED FOR FAST, ENERGY EFFICIENT COMPUTING. SUCH A CHALLENGE TRIGGERS THE WIDESPREAD INTEREST IN DEVELOPING LOGIC-IN-MEMORY HARDWARE, WHERE THE LATENT TIME IN DATA PROCESSING CAN BE EFFECTIVELY MINIMIZED. FOR THIS QUEST, THE TEAM SEEKS TO REALIZE AN ENERGY EFFICIENT LOGIC-MEMORY BIFUNCTIONAL DEVICE. FERROELECTRIC TUNNEL JUNCTIONS (FTJS) ARE A CRITICAL CLASS OF NON-VOLATILE MEMORY DEVICES HOLDING UNIQUE PROMISE BECAUSE THEY CAN BE SEAMLESSLY INTEGRATED WITH THE CONTEMPORARY SILICON CHIP PLATFORM. THE OVERARCHING GOAL OF THIS PROJECT IS TO DEVELOP HIGH-PERFORMANCE, ENERGY-EFFICIENT FTJS FOR IN-MEMORY COMPUTING, BASED ON THE CO-DESIGNED TWO-DIMENSIONAL (2D) VAN DER WAALS FERROELECTRIC MATERIALS, INTERFACES, AND MULTILAYER STACKS. TO REALIZE THIS VISION, THREE MAIN FIGURES OF MERIT FOR THE FTJS NEED TO BE REALIZED IN THE SAME DEVICE: LOW SWITCHING VOLTAGES, HIGH ON/OFF RATIOS, AND HIGH ON-STATE CURRENT DENSITIES. THE TEAM APPLIES FIRST-PRINCIPLES CALCULATION, QUANTUM TRANSPORT SIMULATION, HIGH-QUALITY BULK CRYSTALS AND THIN FILMS SYNTHESIS AND CHARACTERIZATION, AND FTJ NANODEVICES FABRICATION AND CHARACTERIZATION, TO CO-DESIGN 2D FERROELECTRICS WITH LOW COERCIVE FIELD AND OPTIMIZED METAL/2D FERROELECTRICS/GRAPHENE FTJ STACKS WITH HIGH ON/OFF RATIO AND HIGH ON-STATE CURRENT DENSITY. THE TEAM EMPLOYS A CO-DESIGN PHILOSOPHY, WITH A STRATEGIC PLAN TO DEVELOP THE MATERIALS AND DEVICES THROUGH SCALABLE SYNTHESIS AND MANUFACTURING TECHNIQUES. THIS BRINGS THE RESEARCH OUTCOMES OF THIS PROJECT CLOSER TO INDUSTRY-COMPATIBLE REALIZATIONS. THE TEAM CONDUCTS WORKFORCE TRAINING THROUGH WORKSHOPS (E.G., ?QUANTUM + CHIPS? SUMMER PROGRAM), AND TRAINS STUDENTS IN DEVICE PHYSICS AND FABRICATION EXPERTISE THAT ARE CRITICALLY NEEDED FOR A GREATER MICROELECTRONICS WORKFORCE IN THE U.S. THE TEAM?S EDUCATION PLANS ALSO INCLUDE COURSE MATERIAL DEVELOPMENT OUT OF THIS UNIQUE MATERIAL/DEVICE CO-DESIGN RESEARCH AND THE CONTINUED OUTREACH TO STUDENTS OF UNDERREPRESENTED GROUPS BOTH IN CO-PIS? THREE REGIONS AND NATIONALLY. TECHNICAL DESCRIPTION FERROELECTRIC TUNNEL JUNCTIONS (FTJS) ARE CRITICAL NON-VOLATILE MEMORY DEVICES THAT CAN BE SEAMLESSLY INTEGRATED WITH THE SILICON CHIP PLATFORM. THIS INTEGRATION OF FTJS INTO SILICON MICROELECTRONICS CAN FACILITATE THE PHYSICAL PROXIMITY BETWEEN MEMORY AND LOGIC UNITS, THEREBY REDUCING THE CROSS-HARDWARE LATENT TIME AND ENABLING HIGH-SPEED DATA PROCESSING. IF AN FTJ MEMORY CAN ALSO FUNCTION AS A LOGIC DEVICE SUCH AS A TUNNELING FIELD EFFECT TRANSISTOR, IT WOULD THEN BE MEMORY-LOGIC BIFUNCTIONAL. SUCH A TECHNOLOGICAL BREAKTHROUGH WOULD BE MONUMENTAL FOR IN-MEMORY COMPUTING. TO ACHIEVE THIS GOAL, COMPELLING ADVANCES IN FTJS ARE NEEDED. SPECIFICALLY, THREE MAIN FIGURES OF MERIT IN PERFORMANCE AND ENERGY COST SHOULD BE SATISFIED: LOW SWITCHING VOLTAGES (E.G., 10,000,000,000), AND HIGH ON-STATE CURRENT DENSITIES (E.G., > 100,000 AMPERE PER CENTIMETER SQUARE). TO ACHIEVE THESE METRICS, THE TEAM PLANS TO CO-DESIGN 2D VDW FERROELECTRIC MATERIALS, INTERFACES, AND MULTILAYER STACKS, POTENTIALLY LEADING TO THREE ASPECTS OF KNOWLEDGE ADVANCES. FIRST, THE TEAM PLANS TO DEVELOP A NEW SYNTHESIS APPROACH FOR FERROELECTRIC IN2SE3 WITH ?NEGLIGIBLE DEFECTS,? AND USE THESE CRYSTALS TO EXPLORE THE INTRINSIC PROPERTIES (E.G., COERCIVITY) OF 2D FERROELECTRIC CRYSTALS AND THE INTRINSIC ELECTRON TUNNELING BEHAVIOR IN 2D FTJS. SECOND, THIS PROJECT AIMS TO ELUCIDATE THE FUNDAMENTAL RELATIONSHIP BETWEEN 2D FTJS? ON/OFF RATIO AND BASIC MATERIAL PARAMETERS INCLUDING BANDGAPS OF 2D FERROELECTRICS, GRAPHENE LAYER NUMBERS AND DOPING LEVELS, AND METAL WORK FUNCTIONS. THIRD, THIS PROJECT CAN EXPERIMENTALLY MAP OUT THE BAND ALIGNMENT INFORMATION BETWEEN CONVENTIONAL METALS AND 2D FERROELECTRICS, REVEALING THE RELATIONSHIP BETWEEN THE METAL/FERROELECTRIC BAND ALIGNMENT AND THE RESULTING ON-STATE CURRENT DENSITY. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE PLANNED FOR THIS AWARD.
$260.0k 9/10/24