This $865,209 Project Grant awarded by the National Science Foundation's (NSF) Computer and Information Science and Engineering (CISE) Program (CFDA 47.070) supports the development of formal verification methods and tools to improve the correctness and reliability of programmable networking hardware. The project aims to develop novel techniques for mathematically proving the functional correctness of complex optimizations used in high-performance networking switches, such as those developed by Intel. The goal is to enable the semi-automatic derivation of optimized switches that are guaranteed to be correct by construction, reducing the need for extensive testing and auditing to find bugs. The project plans to validate the approach by deriving realistic switch designs and providing tutorials at major networking conferences to facilitate industry adoption of the new formal verification methods. The award period runs from January 15, 2025 to December 31, 2027, and no sub-awards are planned.
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